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Unified gate capacitance model of polysilicon thin-film transistors for circuit applications

Published online by Cambridge University Press:  24 June 2008

W. Deng ,
X. Zheng ,
R. Chen ,
W. Wu  and
Z. An
W. Deng*
Affiliation:
Institute of Microelectronics, South China University of Technology, Guangzhou 510640, P.R. China
X. Zheng
Affiliation:
Institute of Microelectronics, South China University of Technology, Guangzhou 510640, P.R. China
R. Chen
Affiliation:
Institute of Microelectronics, South China University of Technology, Guangzhou 510640, P.R. China
W. Wu
Affiliation:
Institute of Microelectronics, South China University of Technology, Guangzhou 510640, P.R. China
Z. An
Affiliation:
Institute of Microelectronics, South China University of Technology, Guangzhou 510640, P.R. China
*
dwanl@126.com
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Abstract

The characteristics of the gate capacitance at polysilicon thin-film transistors (poly-Si TFTs) based on terms of surface potential have been described and modeled in this paper. An explicit approximate relation for surface potential as a function of terminal voltages is developed. The theory is based on an assumed exponential distribution of trap states in the energy gap. Moreover, the model has been found to give an accurate description of the unique features of poly-Si TFTs, such as rapid increase of C gs in leakage region and C gd in kink region. The good agreement between simulated model results and experimental data confirms the accuracy and efficiency of this model.

Keywords

Type
Research Article
Information
The European Physical Journal - Applied Physics , Volume 43 , Issue 1 , July 2008 , pp. 43 - 49
Copyright
© EDP Sciences, 2008

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