Hostname: page-component-78c5997874-j824f Total loading time: 0 Render date: 2024-11-19T14:42:14.417Z Has data issue: false hasContentIssue false
  • English
  • Français

Measuring The Work Functions Of PVD TaN, TaSiN And TiSiN Films With A Schottky Diode CV Technique For Metal Gate CMOS Applications

Published online by Cambridge University Press:  11 February 2011

James Pan ,
Christy Woo ,
Minh-Van Ngo ,
Bryan Tracy ,
Ercan Adem ,
Stephen Robie ,
Qi Xiang  and
Ming-Ren Lin
James Pan
Affiliation:
Advanced Micro Devices, Sunnyvale, California 95014, U.S.A.
Christy Woo
Affiliation:
Advanced Micro Devices, Sunnyvale, California 95014, U.S.A.
Minh-Van Ngo
Affiliation:
Advanced Micro Devices, Sunnyvale, California 95014, U.S.A.
Bryan Tracy
Affiliation:
Advanced Micro Devices, Sunnyvale, California 95014, U.S.A.
Ercan Adem
Affiliation:
Advanced Micro Devices, Sunnyvale, California 95014, U.S.A.
Stephen Robie
Affiliation:
Advanced Micro Devices, Sunnyvale, California 95014, U.S.A.
Qi Xiang
Affiliation:
Advanced Micro Devices, Sunnyvale, California 95014, U.S.A.
Ming-Ren Lin
Affiliation:
Advanced Micro Devices, Sunnyvale, California 95014, U.S.A.
Get access

Abstract

The metal gate process becomes a promising candidate for sub-65nm CMOS, due to the elimination of polysilicon depletion effects, and the possibility of adjusting the CMOS threshold voltage without more threshold implants. Our goal is to process mteal films with tunable work functions, in order to meet the demand of sub-65nm metal gate CMOS.

PVD TaN films are deposited with various processing conditions. Auger analysis shows that by changing the nitrogen flow rate and the plasma power, the nitrogen content in the TaN films can be adjusted. In order to accurately determine the work function of these TaN materials, we have developed a Schottky Diode CV technique (or Metal-Silicon CV, or MS-CV). This approach not only improves the accuracy of the metal work function measurement, compared with the traditional MOS-CV technique (which is affected by the thickness and quality of the oxide), but also simplifies the fabrication.

With the MS-CV's, we have successfully measured the work functions of Ni and Co, and compared the data with published references. The work function of PVD TaN actually decreases with higher nitrogen content, according to the Auger data and the MS-CV measurement, ranging from 3.42 – 4.20 Volts. The MS-CV technique is shown to be independent to the size of the capacitors, and is little affected by the measurement frequency. By changing the frequency from 100KHz to 1MHz, the error in the work function is less than 50mV.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 745: Symposium N – Novel Materials and Processes for Advanced CMOS , 2002 , N3.2
Copyright
Copyright © Materials Research Society 2003

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

[1] Choi, Y., Lindert, N., Xuan, P., Tang, S., Ha, D., Anderson, E., King, T-J., Bokor, J., Hu, C., “Sub-20nm CMOS FinFET Technologies,” in IEDM Tech. Dig., 2001, pp. 421–424.Google Scholar
[2] Chau, R., Kvalieros, J., Doyle, B., Murthy, A., Paulsen, N., Lionberger, D., Barlage, D., Arghavani, R., Roberds, B. and Doczy, M., “A 50nm Depleted-Substrate CMOS Transistor (DST),” in IEDM Tech. Dig., 2001, pp. 621–624.Google Scholar
[3] Iwai, H., “Advanced Device Technologies,” in VLSI Tech. Dig., 2002, short course pp. 1–87.Google Scholar
[4] Matsuda, S., Yamakawa, H., Azume, A. and Toyoshima, Y., “Performance Improvement of Metal Gate CMOS Technologies,” in VLSI Tech. Dig., 2001, pp63–64.Google Scholar
[5] Lee, C., Lee, J., Bai, W., Bae, S., Sim, J., Lei, X., Clark, R., Harada, Y., Niwa, M. and Kwang, D., “Self-Aligned Ultra Thin HfO2 CMOS Transistors with High Quality CVD TaN Gate Electrode,” in VLSI Tech. Dig., 2002, pp. 82–83.Google Scholar
[6] Yu, B., Wang, H., Xiang, Q., An, J., Jeon, J. and Lin, M-R., “Scaling Towards 35nm Gate Length CMOS,” in VLSI Tech. Dig., 2001, pp. 74–75.Google Scholar
[7] Sze, S., “Physics of Semiconductor Devices,” John Wiley and Sons, Inc. New York, NY, 1981, pp. 251 Google Scholar