Book contents
- Frontmatter
- Contents
- Contributors
- Preface
- Section I CMOS circuits and technology limits
- Section II Tunneling devices
- 5 Designing a low-voltage, high-current tunneling transistor
- 6 Tunnel transistors
- 7 Graphene and 2D crystal tunnel transistors
- 8 Bilayer pseudospin field effect transistor
- Section III Alternative field effect devices
- Section IV Spin-based devices
- Section V Interconnect considerations
- Index
- References
7 - Graphene and 2D crystal tunnel transistors
from Section II - Tunneling devices
Published online by Cambridge University Press: 05 February 2015
- Frontmatter
- Contents
- Contributors
- Preface
- Section I CMOS circuits and technology limits
- Section II Tunneling devices
- 5 Designing a low-voltage, high-current tunneling transistor
- 6 Tunnel transistors
- 7 Graphene and 2D crystal tunnel transistors
- 8 Bilayer pseudospin field effect transistor
- Section III Alternative field effect devices
- Section IV Spin-based devices
- Section V Interconnect considerations
- Index
- References
Summary
What is a low-power switch?
Transistors in the traditional field effect geometry operate by the injection of mobile carriers – electrons or holes – from a source reservoir to the drain reservoir through a conducting channel region. The carriers enter the channel region by surmounting an electrostatic potential barrier. The gate electrode controls the height of this barrier capacitively. The carriers in the source reservoir are in thermal equilibrium with the source contact. This means that the carriers, say electrons, are distributed in energy in the conduction band according to the Fermi–Dirac distribution f(E = 1/1[1+exp((E − EF)/kT)]. The Maxwell–Boltzmann approximation f(E) ~ exp[− E/kT] of the Fermi–Dirac distribution for large energies represents the high-energy tail of the distribution. There are electrons in this tail with energy higher than the potential barrier; the gate cannot stop them from being injected into the channel. This leads to a sub-threshold “leakage” drain current ID ~ exp[qVGS / kT], which leads to the well-known sub-threshold slope (S) requirement of S ~ (kT / q)ln10 ~ 60 mV/dec change of current. Methods to make the SS steeper than the 300 K value of 60 mV/dec value are expected to substantially lower the power dissipation in digital logic and computation [1, 2]. The methods must explore novel mechanisms of charge transport, or of electrostatic gating. This chapter focuses on transport.
The high-energy tail of electrons exists because of the available density of states (DOS) DC(E) of the conduction band; the electron distribution in energy is n(E) = DC(E)f(E). If the DOS were cut off, there would be no tail, and it is possible to obtain S less than 60 mV/dec. This sort of energy filtering is possible if we replace the n-type source for electrons by a p-type source, which has a valence band maximum and zero DOS above. For injection into the channel of the n-FET, the electrons cannot undergo the traditional drift/diffusion process, but have to quantum mechanically tunnel through the bandgap. This energy-filtering scheme to achieve sub-60 mV/dec switching is the central idea behind the tunneling FET (or TFET).
- Type
- Chapter
- Information
- CMOS and BeyondLogic Switches for Terascale Integrated Circuits, pp. 144 - 174Publisher: Cambridge University PressPrint publication year: 2015