CMOS and Beyond: Logic Switches for Terascale Integrated Circuits

doi:10.1017/CBO9781107337886

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CMOS and Beyond

CMOS and Beyond

Logic Switches for Terascale Integrated Circuits

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Chang, Sou-Chi Manipatruni, Sasikanth Nikonov, Dmitri E. and Young, IAN A. 2016. Clocked Domain Wall Logic Using Magnetoelectric Effects. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 2, Issue. , p. 1.

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Edited by Tsu-Jae King Liu, University of California, Berkeley, Kelin Kuhn, Cornell University, New York

Publisher: Cambridge University Press
Online publication date: February 2015
Print publication year: 2015
Online ISBN: 9781107337886
DOI: https://doi.org/10.1017/CBO9781107337886

Subjects: Engineering, Electronic, Optoelectronic Devices, and Nanotechnology, Circuits and Systems

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CMOS and Beyond
Edited by Tsu-Jae King Liu, Kelin Kuhn
Online ISBN: 9781107337886

Book DOI: https://doi.org/10.1017/CBO9781107337886
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Get up to speed with the future of logic switch design with this indispensable overview of the most promising successors to modern CMOS transistors. Learn how to overcome existing design challenges using novel device concepts, presented using an in-depth, accessible, tutorial-style approach. Drawing on the expertise of leading researchers from both industry and academia, and including insightful contributions from the developers of many of these alternative logic devices, new concepts are introduced and discussed from a range of different viewpoints, covering all the necessary theoretical background and developmental context. Covering cutting-edge developments with the potential to overcome existing limitations on transistor performance, such as tunneling field-effect transistors (TFETs), alternative charge-based devices, spin-based devices, and more exotic approaches, this is essential reading for academic researchers, professional engineers, and graduate students working with semiconductor devices and technology.

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CMOS and Beyond

Logic Switches for Terascale Integrated Circuits

This book has been cited by the following publications. This list is generated based on data provided by CrossRef.

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Contents

Frontmatter
pp i-iv

Contents
pp v-xii

Contributors
pp xiii-xiv

Preface
pp xv-xviii

Section I - CMOS circuits and technology limits
pp 1-2

1 - Energy efficiency limits of digital circuits based on CMOS transistors
pp 3-13

2 - Beyond transistor scaling: alternative device structures for the terascale regime
pp 14-38

3 - Benchmarking alternative device structures for the terascale regime
pp 39-55

4 - Extending CMOS with negative capacitance
pp 56-76

Section II - Tunneling devices
pp 77-78

5 - Designing a low-voltage, high-current tunneling transistor
pp 79-116

6 - Tunnel transistors
pp 117-143

7 - Graphene and 2D crystal tunnel transistors
pp 144-174

8 - Bilayer pseudospin field effect transistor
pp 175-206

Section III - Alternative field effect devices
pp 207-208

9 - Computation and learning with metal–insulator transitions and emergent phases in correlated oxides
pp 209-235

10 - The piezoelectronic transistor
pp 236-262

11 - Mechanical switches
pp 263-298

Section IV - Spin-based devices
pp 299-300

12 - Nanomagnetic logic: from magnetic ordering to magnetic computing
pp 301-334

13 - Spin torque majority gate logic
pp 335-358

14 - Spin wave phase logic
pp 359-378

Section V - Interconnect considerations
pp 379-380

15 - Interconnect considerations
pp 381-412

Index
pp 413-420

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CMOS and Beyond

Logic Switches for Terascale Integrated Circuits

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