Introduction

The bilayer pseudospin field effect transistor (BiSFET) is intended to enable much lower voltage and power operation than possible with complementary metal–oxide–semiconductor (CMOS) field effect transistor (FET)-based logic [1, 2]. The ultimate limits of CMOS are not due to fabrication technology limitations. Rather, they are intrinsic to its operating principles, defined by basic physics such as charge carrier thermionic emission over the channel barrier and quantum mechanical tunneling through it. New operating principles are required. The BiSFET relies on the possibility of room temperature excitonic (electron-hole) superfluid condensation in two dielectrically separated graphene layers [3, 4]. While the physics is interesting in its own right, from the device point of view this many-body physics brings with it the possibility of a strong sensitivity to sub-thermal voltages (sub-kBT/q voltages, where kB is Boltzmann’s constant, T is the temperature in Kelvin, and q is the magnitude of electron charge) in the current–voltage (I–V) characteristics [5–7]. With power consumption proportional to the square of voltage, use of voltages on the scale of or less than room temperature kBT/q ≈ 26 mV offers order of magnitude reductions in switching energies as compared to even end-of-the roadmap CMOS [8]. Circuit simulation with 25 mV power supplies show switching energies on the scale of 10 zeptojoules (zJ) per BiSFET (where 1 zJ = 10–21 J = 10–3 aJ)! However, with this potential for voltage reduction also come I–V characteristics much different from those of MOSFETs that must be worked around at worst, and may provide new circuit opportunities at best. In terms of interconnects, information would continue to be passed via charge among devices. In this way, BiSFETs would also be compatible with existing electronic devices after voltage level shifts.