There are a variety of different mechanisms which may contribute to the plastic deformation of a polycrystalline material, involving such processes as dislocation glide, dislocation climb, grain boundary sliding and diffusion of vacancies. Each mechanism can be characterized by a relationship which gives strain-rate as a function of stress, temperature and microstructural state. A deformation mechanism may actually involve multiple, coupled atomic processes. For example, diffusional creep results from the coupled operation of vacancy diffusion and grain boundary sliding. The total strain-rate of the polycrystal is the sum of the contributions of the various different mechanisms, with different mechanisms dominant in different regimes of stress and temperature. In bulk polycrystals this behavior has been described with deformation-mechanism maps. For thin films the same atomic processes of deformation can operate, but the deformation mechanisms may have different stress---strain-rate---temperature relationships because of the presense of free surfaces or thin-film---substrate interfaces.

As the shrinking of VLSI devices continues, the problem of voids in interconnections becomes of steadily increasing concern. Voids can result from the effects of triaxial tensile stresses produced during fabrication; they can also arise from electromigration. The effects can combine: voids arising from mechanical stress can move and grow under electromigration stress. A detailed understanding of the phenomena requires both knowledge of the properties of the metal and dielectric as functions of time and temperature, and direct observations of the void behavior in real time under varying stress conditions. The material property information can be obtained by a combination of wafer curvature, X-ray diffraction and ultramicro indentation measurements. Void behavior can be inferred from high precision resistivity measurements, and observed directly with Scanning Electron Microscopy. With these data it is possible to evaluate various models for the phenomena.

Based on recent theoretical progress we discuss current and potential new remedies for thermal stress and electromigration induced damage and failure in microelectronic interconnects. We present a new idea involving the patterning of alternately adhering and non-adhering interfaces between metal and surroundings, and briefly discuss the potential for predicting failure and/or extrapolating accelerated test results to service conditions and into the so-called ‘six-sigma’ range.

Using a 120 kV STEM equipped with a backscattered electron detector and operated as a conventional SEM. voids in metal lines can be detected through 1 μm of passivation. By applying current to passivated thin metal lines while in the microscope, voids can be observed while electromigration is in progress. Voids move significant distances during electromigration. On at least some occasions. failure of the line is not the result of a void growing until the width of the line is reached. On these occasions, when the size of the void approaches the width of the line. the void breaks up into smaller voids.

Stress-induced voiding is an important reliability concern in narrow aluminum based metallizations used as interconnects in very large scale integrated circuits. The thermal stresses that arise in the interconnects after excursions to elevated temperatures are tensile and extremely high. Void nucleation is commonly found to take place at the line edges where the stress is highest. In lines of rectangular cross section, in particular, there arise shear stresses at line edges and corners which can be higher than the dilational stress components. In this paper we consider analytically the stress states arising in interconnect lines of rectangular cross section. We argue that void nucleation is likely to be connected to the high shear stress at the edges and corners, facilitating grain boundary sliding.

A model is proposed for stress voiding in passivated thin film conductors. The rate limiting step is argued to be the formation of vacancies at dislocation jogs which then diffuse to void sites.

In our development of a reliability circuit simulator, capable of indicating the most vulnerable spots for failure caused by electromigration, we use two levels: circuit and physical level. On circuit level a new approach towards reliability called the stressor/susceptibility method is used. On physical level 2D electromi.ration simulations can be performed on metallization structures. The atomic redistribution and the consequent resistance change due to electromigration can be calculated.

Time-dependent vacancy concentration profiles are calculated numerically as solutions to the electromigration transport equation under dc and pulsed dc current stress conditions in finite-length conductors. An electromigration model based on the buildup of a critical vacancy supersaturation to initiate failure agrees well with several reported experimental observations.

Bimodal electromigration-induced open failure time distributions are reported for both single-level and double-level interconnect structures due to inherent microstructural variations. For flat interconnect lines, the bimodality arises when some lines in a test population have only bamboo boundaries, and other lines contain some triple junctions as well as bamboo boundaries. For via structures, two failure mechanisms result if some of the vias are not in contact with grain boundaries in the underlying metal, and others are. For both lines and vias, a large apparent deviation in failure times, σ, is a signal of a possible bimodal distribution, which can also be confirmed by microscopic examinations, resistance measurements, or an investigation of the metal microstructure. Insufficient testing can result in an incorrect asumption of a monomodal failure distribution, leading to either optimistic or pessimistic reliability predictions, depending on the size of the test sample population and the degree to which the test population is representative of the actual overall population.

Grain growth is the key process in the development of the microstructure of deposited metal films. Grain boundaries in turn exert a dominant influence on the properties of interconnects in integrated circuits. In addition to the practical importance of the phenomena, grain growth in films is of considerable fundamental interest because of the possibility of comparing the predictions of models with observations. The thermodynamic basis for the limiting grain size resulting from grain growth in sheets (or films) was laid by Mullins and subsequently cxtcndcd by Walton et al. to the case of interconnects. In their treatments grain growth stagnates when the forces resulting form the grain boundary excess energy are balanced by the pinning force resulting from grooving. Surface energy anisotropy can drastically modify this equilibrium and even lead to the result that there is no limiting grain size. The basic phenomenology of grain growth in films has been modelled and investigated experimentally. In situ experiments provide a direct comparison with models and confirm many of the predictions based on models. Specifically in the context of lines the effects of grooving on the top and side surfaces are predicted to result in a critical ratio of width to thickness above which a fully bamboo structure cannot be achieved. This is verified by observations.

The microstructure in narrow (1.1, 1.5 and 2.1 μm) unpassivated lines of Al-4wt.% Cu is found to be ‘near-bamboo’, with Al2Cu grains being a significant feature correlated with thermal hillocking and with the development of damage on electromigration. The development of damage is shown to be closely related to the median time to failure, with its initiation being at a rate proportional to the square of the current density. The mechanisms of damage development are discussed, with particular reference to near-bamboo, two-phase microstructures.

We have developed a new experimental technique to study electromigration in bicrytal Al lines as a function of the type and location of the grain boundary as well as the testing temperature. The failure times of these lines are found to be lognormally distributed. The median time to failure (MTTF) depends more strongly on the boundary orientation than the type of grain boundary. The dependence of lifetimes on the type and orientation of grain boundaries, the location and appearance of the failure sites, and the measured activation energy (E.) of 0.94eV suggest that both interfacial and grain boundary diffusion contribute to failure in bicrystal lines, and likely in bamboo and near-bamboo lines as well.

We report a statistical analysis of electromigration (EM) induced damage and failure in unpassivated 1.4 mm long Al-4wt%Cu interconnects. The populations of damage sites of various types observed microscopically in life-tested samples are correlated with track width (1.1, 1.5 and 2.1 μm), temperature (200, 230, 260 and 300°C), current density (1, 2 and 3 × 1010 A m−2) and lifetest data. Some implications for damage and failure mechanisms are discussed.

A strong correlation was found between film texture, quantified as fiber plots of (111) intensity versus tilt angle from the normal direction, and the resulting electromigration behavior of layered Ti/AlCu/Ti films. Superior electromigration behavior was found for those films which had a low volume fraction of randomly oriented grains, strong and sharp texture. Film microstructure and electromigration lifetime data on DC magnetron sputtered and electron gun evaporated AI-Cu and layered fine lines, fabricated and tested in the same laboratory, are included for a direct comparison. Outstanding electromigration lifetimes were measured for sputtered, layered, submicron films with copper concentrations between 0.12 - 2wt.%Cu. In contrast the electromigration lifetimes of evaporated layered films were found to degrade rapidly at < 2wt.%Cu. This anomalous electromigration behavior was attributed to both film texture and subtle structural differences in the Ti-Al intermetallics formed.

Pure aluminum film was deposited on oxidized silicon to develop three different conditions for study. Grain size and grain size distribution were the same for all cases isolating texture as the major microstructural variable. Electromigration tests were done on 1.8pm thick lines at Ix106 A/cm2 at several temperatures between 150°C and 250°C. Over the entire temperature range a strong (111) texture improves the median time to failure. The applicability of a log normal fit to the failure distribution is questioned because the sites that are susceptible to electromigration damage vary in a statistical fashion, sometimes giving what appears to be a bimodal failure distribution. Activation energy is also a function of texture but depends on the applicability of the log normal failure distribution to give values that can be correlated with transport processes.

Electromigration in metal interconnect lines produces sites of damage, such as voids, hillocks and whiskers, which by definition are the sites of flux divergence in the lines. Detailed observations of damage volume and morphology, especially in relation to the local microstructure, may yield vital information about the processes which produce the damage and ultimate failure in the interconnects. We present fractographic measurements of void volumes and the spacing between voids and corresponding hillocks in Al and Al-2% Cu interconnects which have been electromigration tested until failure. It is shown that the void density as well as the shape of failure voids depend on the current density. Further it is found that the distribution of the spacings between voids and corresponding hillocks changes as a function of current density.

We have previously shown greatly enhanced resistance to stressinduced hillock formation through fluorine incorporation in aluminum films. Utilizing relatively low F incorporation (<0.1 atomic %), hillock formation density is reduced ∼10x over pure or similarly Cu-doped aluminum films. Electromigration tests were performed on a matrix of structures with varying topology (step heights and slopes) and fluorine incorporation dose. We find that although F improves the stress-induced hillock formation by an order of magnitude, the electromigration performance of flat structures is only slightly improved with F incorporation. Analyzing various step heights and step slopes, the nonfluorinated Al experienced a decreasing electromigration lifetime with increasing step height. However, the optimally implanted F samples showed almost no lifetime reduction with step coverages over a similar regime. In addition, scanning electron micrographs of the failed samples revealed that the failures of the fluorinated samples differ markedly from the non-fluorinated samples. Finally, SIMS profiles taken on F and Cu (for comparison) implanted samples reveal the fundamentally different nature of the two beneficial components: Cu redistributes relatively easily throughout the Al film to segregate to grain boundaries. In contrast, the F profile is extremely stable with simnilar anneals and provides its beneficial effect by forming a distributed refractory metal-like structure within the interconnect.

The range of microstructural effects on thin film and interconnect properties is briefly described, and the improvement of interconnect reliability with increased strength is reviewed. We show that the strengthening effect of dispersed second phases depends on their resistance to coarsening during thermal treatments. The rapid coarsening of Θ phases during annealing and accelerated electromigration testing is reviewed, leading to a discussion of metallurgical factors which determine the coarsening behavior. We describe alloy systems expected to have reduced coarsening rates. We suggest that the recently reported increased reliability of Al-Sc interconnects is due to finely dispersed coherent phases which are particularly resistant to coarsening. The range of electromigration failure morphologies is illustrated with particular emphasis on transgranular slit failures. The failures are discussed in terms of diffusion pathways and models for failure.

Silicon device performance has improved dramatically over the past two decades. During that time, the portion of total circuit delay attributable to interconnect wiring has increased to nearly half. Changes in the use of aluminum wiring and silicon oxide insulators must be considered to further improve performance.

The generation of ULSI circuitry now under development in the industry depends heavily on innovations in materials and processes to achieve significant improvements in wiring density and circuit performance. The subsequent generation places even greater demands on materials improvements for lower resistivity wiring and a lower dielectric constant insulator. Integrating materials and methods compatible with semiconductor processing while ensuring device reliability will create a significant financial challenge in addition to the technical challenge.

This presentation enumerates the interconnection challenges facing the materials scientist and the circuit designer. The ultimate limits in materials improvements are predictable and finite. Further improvements will be derived from design innovations such as treating interconnects as active rather than passive devices. Accurate physical modelling of MLM structures will complement even more complex electrical modelling. Manufacturing sciences will grow in sophistication if implementation is to succeed. The financial burden of these technical challenges will foster collaborations among semiconductor manufacturers, equipment vendors, and research universities.

Thermal stability of evaporated Pd, Pt and Rh films as reaction barriers to Au-Sn solder was studied for the application to flip-chip optoelectronic integration. Sn in the solder diffused preferentially into a barrier metal uniformly to produce more stable intermetallic phases for all three metals. Pt and Rh exhibited sufficiently samll interdiffusion coefficients with high activation energies in the temperature range of device operation (Pt: 1.35 eV, Rh: 1.95 eV). This result demonstartes the usefulness of Pt and Rh in practical flip-chip integrated circuit fabrication. Aging test was conducted on flip-chip GaInAs/InP p-i-n photodiodes with Au-Sn/Pt metallization and no severe degradation was observed over 3400 h at 180 ° C. The same metallization techniques were applied in the fabrication of 10 Gbps optoelectronic integrated receivers as well as quad p-i-n photodiodes for coherent optical receivers.