Devices fabricated from the wide bandgap semiconductor SiC have many advantages over those made from conventional semiconductors. Thus, performance characteristics of some 4H-SiC devices can be two orders of magnitude better than equivalent devices made from silicon. On the other hand, new and unexpected problems have emerged with the operation of some SiC devices that need to be understood and solved before further progress can be made in this area. One of the most intriguing problems has been the degradation of bipolar PiN diodes that have major advantages over unipolar Schottky barrier diodes at high blocking voltages. The electrical degradation of the PiN diodes refers to a drop in voltage under extended forward current operation. The degradation appears to be associated with the appearance of stacking faults (SFs) in the entire base region of the diode. In this paper, we discuss some puzzling aspects of stacking fault formation in such diodes. Electroluminescence as well as TEM has been used to investigate the degradation problem and, based on experimental results, the formation of stacking faults within the device, possible sources of partial dislocations responsible for the stacking faults, and the enhanced motion of dislocations under forward biasing are considered.

The early development of stacking faults in SiC PiN diodes fabricated on 8° off c-axis 4H wafers has been studied. The 150μm drift region and p-n junction were epitaxially grown. The initial evolution of the stacking faults was examined by low injection electroluminescence using current-time product steps as low as 0.05 coul/cm2. The properties of the dislocations present before electrical stressing were determined based on previously observed differences of Si-core and C-core partial dislocations and the patterns of stacking fault expansion. The initial stacking fault expansion often forms a chain of equilateral triangles and at higher currents and/or longer times these triangles coalesce. All of the faulting examined in this paper originated between 10 and 40 μm below the SiC surface. The expansion rate of the bounding partial dislocations is very sensitive to the partials' line directions, their core types and the density of kinks. From these patterns it is concluded that the stacking faults originate from edge-like basal plane dislocations that have Burgers vectors either parallel or anti-parallel to the off-cut direction. Evidence for dislocation conversions between basal-plane and threading throughout the epitaxial drift region is also presented.

We have investigated the formation and current-voltage characteristics of Si-dots/SiC multilayer heterostructures on p+Si(100) substrates by means of supersonic free-jet chemical vapor deposition using a single gas source CH3SiH3. Si-dots were successfully deposited on epitaxial SiC thin films on Si(100) with assistance of a tungsten hot filament. Negative deferential resistance was observed in the current-voltage curve of SiC/Si-dot/SiC measured by an atomic force microscope using a gold-coated conductive cantilever. The observed current-voltage characteristics can be attributed to the hole resonant tunneling through the SiC double barriers.