Hostname: page-component-78c5997874-fbnjt Total loading time: 0 Render date: 2024-11-19T18:04:17.006Z Has data issue: false hasContentIssue false
  • English
  • Français

Delay modeling of high-speed distributed interconnect for the signal integrity prediction

Published online by Cambridge University Press:  15 February 2012

B. Raveloa
B. Raveloa*
Affiliation:
IRSEEM (Research Institute in Electronic and Embedded Systems), EA 4353, Graduate School of Engineering ESIGELEC, Technopole du Madrillet, Avenue Galilée, BP 10024, 76801 Saint Etienne du Rouvray Cedex, France
*
ae-mail: blaise.ravelo@yahoo.fr
Get access

Abstract

A relevant modeling-method of distributed interconnect line for the high-speed signal integrity (SI) application is introduced in this paper. By using the microwave and transmission line (TL) theory, the interconnect lines are assumed as its distributed RLC-model. Then, based on the transfer matrix analysis, the second-order global transfer function of the interconnect network comprised of the TL driven by voltage source including its internal resistance and the impedance load is expressed. Thus, mathematical analysis enabling the physical SI-parameters’ extraction was established by using the transient response of the loaded line. To verify the relevance of the developed model, RC- and RLC-lines excited by square-wavepulse with 10-Gbits/s-rate were investigated. So, comparisons with SPICE-computations were performed. As results, transient responses perfectly well correlated to the reference SPICE-models were evidenced. As application of the introduced model, evaluations of rise-/fall-times, propagation delays, signal attenuations and even the settling times were realized for different values of TL-parameters. Compared to other methods, the computation execution time and data memory consumed by the program implementing the proposed delay modeling-method algorithm are much better.

Type
Research Article
Information
The European Physical Journal - Applied Physics , Volume 57 , Issue 3 , February 2012 , 31002
Copyright
© EDP Sciences, 2012

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

Kilby, J.S., IEEE Trans. Electron Devices 23, 648 (1976)CrossRef
Moore, G.E., Electron. Mag. 38, 114 (1965)
Moore, G.E., Progress in digital integrated electronics, in Proc. of the IEEE Int. Electron. Devices Meeting, 1975, vol. 21, p. 11Google Scholar
Moore’s Law [Online], http://www.intel.com/museum/archives/historydocs/mooreslaw.htm; Sharma, D.K., Kaushik, B.K., Sharma, R.K., J. Eng. Des. Technol. 9, 63 (2011)Google Scholar
Magen, N., Kolodny, A., Weiser, U., Shamir, N., Interconnect-power dissipation in a microprocessor, in Proc. of the ACM Int. Workshop on System Level Interconnect Prediction, Paris, France, 2004, pp. 7–13Google Scholar
Li, X.-C., Mao, J.-F., Huang, H.-F., Liu, Y., IEEE Trans. Electron. Devices 52, 2272 (2005)CrossRef
Sayed, M.A., Maksoud, E.Y.A., Int. J. Open Problems Compt. Math. 2, 383 (2009)
Voutilainen, M., Rouvala, M., Kotiranta, P., Rauner, T., Multi-Gigabit serial link emissions and mobile terminal antenna interference, in Proc. of 13th IEEE Workshop on Signal Propagation on Interconnects (SPI), Strasbourg, France, 2009Google Scholar
Sato, T., Cao, Y., Agarwal, K., Sylvester, D., Hu, C., IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22, 560 (2003)CrossRef
Hasan, S., Palit, A.-K., Anheier, W., Equivalent victim model of the coupled interconnects for simulating crosstalk induced glitches and delays, in Proc. of 13th IEEE Workshop on Signal Propagation on Interconnects (SPI), Strasbourg, France, 2009Google Scholar
Maichen, W., When digital becomes analog-interfaces in high speed test, Tutorial course, in Proc. of 12th IEEE Workshop on Signal Propagation on Interconnects (SPI), Avignon, France, 2008Google Scholar
Scogna, A.C., Orlandi, A., Ricciuti, V., Signal and power integrity performances of striplines in presence of 2D EBG planes, in Proc. of 12th IEEE Workshop on Signal Propagation on Interconnects (SPI), Avignon, France, 2008Google Scholar
Champac, V., Avendano, V., Figueras, J., IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18, 256 (2010)CrossRef
Eudes, T., Ravelo, B., Louis, A., PIER J. 112, 183 (2011)CrossRef
Ravelo, B., Eudes, T., Int. J. Numer. Model. (to be published), DOI: 10.1002/jnm.838CrossRef
Eudes, T., Ravelo, B., Louis, A., IEEE Trans. Electromagn. Compat. (to be published), DOI: 10.1109/TEMC.2011.2165216CrossRef
Elmore, W.C., J. Appl. Phys. 19, 55 (1948)CrossRef
Wyatt, L., Circuit Analysis, Simulation and Design (North-Holland, Elsevier Science, The Netherlands, 1978)Google Scholar
Wyatt, J.L. Jr., VLSI Memo 145 (1983)
Wyatt, J.L. Jr., Yu, Q., Signal delay in RC meshes, trees and lines, in Proc. of the IEEE Int. Conf. on Computer-Aided Design (ICCAD), Santa Clara, CA, 1984, pp. 15–17; also VLSI Memo, 1984, pp. 84–198Google Scholar
Deutsch, A., IBM J. Res. Devel. 34, 601 (1990)CrossRef
Deschacht, D., Impact of inductance and routing orientation on timing performances of coupled interconnect lines, in Proc. of the 2010 Int. Conf. on Design Technology of Integrated Systems in Nanoscale Era, DTIS’2010, Hammamet, Tunisia, 2010Google Scholar
Kahng, A.B., Muddu, S., IEEE Trans. Comp. Aid. Des. 16, 1507 (1997)CrossRef
van Ginneken, L.P.P.P., Buffer placement in distributed RC-tree network for minimal Elmore delay, in Proc. of the IEEE Int. Symposium of Circuits and Systems (ISCAS), New Orleans, Louisiana, 1990, pp. 865–868Google Scholar
Adler, V., Friedman, E.G., IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process. 54, 607 (1998)CrossRef
Ligocka, A., Bandurski, W., Effect of inductance on interconnect propagation delay in VLSI circuits, in Proc. of 8th Workshop Signal Propagation on Interconnects (SPI), Heidelberg, Germany, 2004, pp. 121–124Google Scholar
Chandel, R., Sarkar, S., Agarwal, R.P., Microelectron. Int. 22, 43 (2005)CrossRef
Ismail, Y.I., Friedman, E.G., Neves, J.L., IEEE Trans. Comp. Aid. Des. 19, 83 (2000)CrossRef
Ismail, Y.I., Friedman, E.G., IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 8, 195 (2000)CrossRef
Hanumolu, P.K., Wei, G.Y., Moon, U.K., Int. J. High Speed Electron. Syst. 15, 429 (2005)CrossRef
Ravelo, B., Perennec, A., Le Roy, M., in VLSI, edited by Wang, Z. (INTECH Book, 2010), pp. 409434, Chap. 20Google Scholar
Eudes, T., Ravelo, B., Appl. Phys. Res. 3, 81 (2011)CrossRef
Ravelo, B., Electromagnetics 31, 537 (2011)CrossRef
Ravelo, B., Eur. Phys. J. Appl. Phys. 55, 1 (2011)CrossRef
Nieuwoudt, A., Kawa, J., Massoud, Y., IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18, 378 (2010)CrossRef
Lehtonen, T., Wolpert, D., Liljeberg, P., Plosila, J., Ampadu, P., IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18, 527 (2010)CrossRef
Chen, D., Cong, J., Fan, Y., Wan, L., IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18, 564 (2010)CrossRef
Carloni, L.P., Kahng, A.B., Muddu, S.V., Pinto, A., Samadi, K., Sharma, P., IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18, 679 (2010)CrossRef
Achar, R., Advanced modeling and simulation methodologies for signal integrity analysis, in Int. Conf. on Recent Advances in Microwave Theory and Applications (MICROWAVE 2008), Jaipur, India, 2008, pp. 279–279Google Scholar
Agilent EEsof EDA, Overview: Electromagnetic Design System (EMDS), (0Sep, 2008) [Online]. http://www.agilent.com/find/eesof-emds
Ansoft Corporation, Simulation software: Highperformance signal and power integrity, Internal Report, 2006
ANSYS, Unparalleled advancements in signal- and power-integrity, electromagnetic compatibility testing (0June 2009) [Online], http://investors.ansys.com/
North East Systems Associates (NESA, RJ45 interconnect signal integrity (2010 CST Computer Simulation Technology AG) [Online]. http://www.cst.com/Content/Applications/Article/Article.aspx?id~=~243
Davis, J.A., Meindl, J.D., IEEE Trans. Electron Devices 47, 2068 (2000)CrossRef
Corless, R.M., Gonnet, G.H., Hare, D.E.G., Jeffrey, D.J., Knuth, D.E., Adv. Comput. Math. 5, 329 (1996)CrossRef
Jeffrey, D.J., Hare, D.E.G., Corless, R.M., Math. Scientist 21, 1 (1996)