Hostname: page-component-7bb8b95d7b-s9k8s Total loading time: 0 Render date: 2024-09-25T14:23:27.977Z Has data issue: false hasContentIssue false

Polysilicon Grain Growth by Rapid Isothermal Annealing

Published online by Cambridge University Press:  21 February 2011

R. F. Pinizzotto
Affiliation:
Ultrastructure, Inc., Richardson, Texas
F. Y. Clark
Affiliation:
Ultrastructure, Inc., Richardson, Texas
S. D. S. Malhi
Affiliation:
Texas Instruments Inc., Dallas, Texas
R. R. Shah
Affiliation:
Texas Instruments Inc., Dallas, Texas
Get access

Abstract

one method of reducing the area occupied by a RAM cell is to stack the p- and n-channel devices on top of one another. This “stacked CMOS” structure is a first step towards three dimensional integration. The simplest approach is to use polysilicon as the substrate for the top transistors. This paper describes the results of grain growth studies of samples annealed by rapid isothermal annealing. The temperature varied from 1100 to 1400°C and the anneal time varied from 10 to 480 seconds. TEM was used to examine the microstructure of the material. The grain growth was found to be film thickness limited, i.e. the final grain size was approximately the same as the initial film thickness. As a result, the kinetics of grain growth cannot be described by a simple logarithmic time law. There also is a velocity dependent drag contribution to the growth kinetics that implies impurities play an important role. The interlevel oxide thickness affects grain growth. Thicker oxides lead to faster growth, probably by reducing the heat flow to the silicon substrate. A capping layer was found to have no effect on the grain size. The above results indicate that it is possible to obtain large grains in short times using isothermal annealing. This process may be useful for fabricating stacked polysilicon layers in three-dimensional integrated circuits.

Type
Research Article
Copyright
Copyright © Materials Research Society 1984

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Malhi, S.D.S., Chatterjee, P.K., Pinizzotto, R.F., Lam, H.W., Chen, C.E.C., Shichijo, H., Shah, R.R. and Bellavance, D.W., ”P-Channel MOSFETs in LPCVD Polysilicon,” IEEE Elec. Dev. Lett., EDL–4(1983)369.Google Scholar
2. Malhi, S.D.S., Shah, R.R., Chatterjee, P.K., Lam, H.W., Pinizzotto, R.F., Chen, C.E.C., Shichijo, H. and Bellavance, D.W., ”Effects of Grain Boundary Passivation on the Characteristics of p-Channel MOSFETs in LPCVD Polysilicon,” Elec. Lett., 19(1983)993.10.1049/el:19830674CrossRefGoogle Scholar
3. Kamins, T.I., ”Hall Mobility in Chemically Deposited Polycrystalline Silicon,” J. Appl. Phys., 42(1971)4357.Google Scholar
4. Depp, S.W., Juliana, A. and Hugh, B.G., ”Polysilicon FET Devices for Large Area Input/Output Applications,” IEDM Technical Digest, (1980)703.CrossRefGoogle Scholar
5. Colinge, J.P., Demoulin, E. and Morel, H., ”Field Effect in Large Grain Polysilicon Transistors,” IEDM Technical Digest, (1982)444.Google Scholar
6. Gibbons, J.F. and Lee, K., ”A One Gate Wide CMOS Inverter,” Electron Device Lett., EDL–1 (1980)117.Google Scholar
7. Colinge, J.P., Demoulin, E. and Lobet, M., ”Stacked Transistors CMOS (ST-CMOS), and NMOS Technology Modified to CMOS,” IEEE Trans. Electron Devices, ED–29(1982)585.Google Scholar
8. For a recent review, see Sedgwick, T.O., ”Short Time Annealing,” J. Electrochem. Soc., 130(1983)484.10.1149/1.2119736Google Scholar
9. Tsaur, B.Y., Donnelly, J.P., Fan, J.C.C. and Geis, M.W., ”Transient Annealing of Arsenic-Implanted Silicon Using a Graphite Strip Heater,” Appl. Phys. Lett., 39(1981)93.Google Scholar
10. Fulks, R.T., Russo, C.J., Hanley, P.P. and Kamins, T.I., ”Rapid Isothermal Annealing of Ion Implantation Damage Using a Thermal Radiation Source,” Appl. Phys. Lett., 39(1981)604.10.1063/1.92818Google Scholar
11. Hu, S.M., ”Defects in Silicon Substrates,” J. Vac. Sci. Tech., 14(1977)17.Google Scholar
12. Billig, E., ”Some Defects in Crystals Grown from the Melt. I. Defects Caused by Thermal Stresses,” Proc. Royal Soc., A235(1956)37.Google Scholar
13. Grey, E.A. and Higgins, G.T., ”A Velocity Independent Drag During Grain Boundary Migration,” Scripta Met., 6(1972)253.Google Scholar
14. Grey, E.A. and Higgins, G.T., ”Solute Limited Grain Boundary Migration: A Rationalisation of Grain Growth,” Acta Met., 21(1973)309.Google Scholar
15. Colinge, J.P., Demoulin, E., Delannay, F., Lobet, M. and Temerson, J.M., “Grain Size and Resistivity of LPCVD Polycrystalline Silicon Films,” J. Electrochem. Soc., 128(1981)2009.10.1149/1.2127785Google Scholar
16. Mei, L., Rivier, M., Kwark, Y. and Dutton, R.W., ”Grain-Growth Mechanisms in Polysilicon,” J. Electrochem. Soc., 129(1982)1791.Google Scholar