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The Impact of the Extrinsic Device on HFET Performance

Published online by Cambridge University Press:  26 February 2011

David R. Greenberg
Affiliation:
Department of Electrical Engineering and Computer Science, Rm. 13–3018, Massachusetts Institute of Technology, Cambridge, MA 02139
Jesús A. Del Alamo
Affiliation:
Department of Electrical Engineering and Computer Science, Rm. 13–3018, Massachusetts Institute of Technology, Cambridge, MA 02139
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Abstract

The extrinsic device is known to degrade the performance of heterostructure field-effect transistors (HFET's) through the introduction of a parasitic source resistance (Rs). To date, however, there has been no recognition of the fact that carrier velocity saturation (vsat) can occur in both the extrinsic source and drain, setting the ultimate limit on maximum drain current (I,D,max) and on the useful VGS swing in HFET's. In this study, we demonstrate the mechanisms through which vsat in the extrinsic device limits device performance, using AlGaAs/n+-InGaAs Metal-Insulator-Doped-channel FET's (MIDFET's) as a vehicle. These devices show that gm falls at a lower VGSthan does fT, by as much as 1 V. This reveals that there are two mechanisms at work. The approach of vsat in the extrinsic source first causes the small-signal source resistance (Ts)to rise rapidly, leading gm to decline but leaving fT unaffected. As the carrier velocity in the extrinsic device approaches Vsat more closely, there is an actual decline of the carrier velocity in the intrinsic device. This process degrades velocity-related figures of merit such as and fT.

Type
Research Article
Copyright
Copyright © Materials Research Society 1992

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References

REFERENCES

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