Hostname: page-component-78c5997874-t5tsf Total loading time: 0 Render date: 2024-11-19T13:17:55.030Z Has data issue: false hasContentIssue false
  • English
  • Français

Control of Amorphous Silicon Crystallization Using Germanium Deposited by Low Pressure Chemical Vapor Deposition

Published online by Cambridge University Press:  17 March 2011

Masato Toita ,
Pranav Kalavade  and
Krishna C. Saraswat
Masato Toita
Affiliation:
Asahi Kasei Microsystems Co. Ltd., Tokyo 151-0053, JAPAN
Pranav Kalavade
Affiliation:
Department of Electrical Engineering, Stanford University, Stanford, CA 94305-4070
Krishna C. Saraswat
Affiliation:
Department of Electrical Engineering, Stanford University, Stanford, CA 94305-4070
Get access

Abstract

Crystallization behavior of 100nm amorphous silicon film with and without a 160nm poly-Ge layer on top was investigated. Ge was observed to increase the nucleation rate as well as to increase the incubation time for nucleation in a-Si. Activation energy for nucleation was 2.3eV for Ge-covered Si films as compared to 2.7eV for the control a-Si films with no poly-Ge. Activation energy for incubation is almost unchanged for both the films (-3.3eV). An alternative seeding technique for a-Si films using the increase in the incubation time for nucleation due to presence of poly-Ge is proposed.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 609: Symposium A – Amorphous & Heterogeneous Silicon Thin Films – 2000 , 2000 , A9.5
Copyright
Copyright © Materials Research Society 2000

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Subramanian, V., Toita, M., Ibrahim, N. R., Souri, S. J. and Saraswat, K. C., IEEE Electron Device Lett. Vol. 20, No. 7, 341 (1999)Google Scholar
2. Wang, A. W. and Saraswat, K. C., Tech. Dig. Int. Electron Devices Meet., 277 (1998)Google Scholar
3. Lee, S-W. and Joo, S-K., IEEE Electron device Lett., Vol. 17, 160 (1996)Google Scholar
4. Subramanian, V. and Saraswat, K. C., IEEE Trans. Electron Device, Vol.45, No.9, 1934 (1998)Google Scholar
5. Naito, S. and Nakashizu, T., Defect Engineering in Semiconductor Growth, Processsing and Device Technology, Proc. Mat. Res.Soc., 641 (1992)Google Scholar
6. King, T-J. and Saraswat, K. C., IEEE Trans. Electron Devices, Vol.41, No.9, 1581 (1994)Google Scholar
7. Kim, J. H., Lee, J. Y., Kim, H. S., Song, Y-H. and Nam, K-S., IEEE Electron Device Lett., Vol. 17, No.5, 205 (1996)Google Scholar