A study of the oxidation kinetics of lightly doped (100) silicon in dry oxygen has been carried out at different pressures (0.03 atm. to 1.0 atm.) and temperatures (900ºC to 1200ºC) for short times (< 500 seconds). The data can be fit equally well to the parabolic model as it can to the linearparabolic or parallel oxidation models. The activation energy derived from analysis of the parabolic rate constant is 0.94 eVand is the same at 1.0 and 0.1 atmosphere dry O2. It was also found that the parabolic rate constant displayed a linear dependence on the O2 pressure.

The electrical characteristics of ultrathin oxynitride gate dielectrics prepared by in-situ multiple rapid thermal processing in reactive ambients (O2 and NH3) have been studied. Specifically, the conduction mechanism, charge trapping properties, time-dependent breakdown, and interface hardness in oxynitride films have been characterized as a function of both RTO and RTN processing parameters. In addition, N-channel MOSFET's have been fabricated using oxynitrides as gate dielectrics and their hot carier immunity has been examined and compared with devices with pure thermal oxides. Devices with superior electrical characteristics and reliability have been produced by optimizing RTO/RTN parameters.

Rapid thermal oxidation (RTO) of Si using transient linearly-ramped-temperature saw-toothed (LRT-ST) and triangular (LRT-TA) thermal cycles has been examined through evaluations of the process uniformity, slip dislocation patterns, and electrical characteristics of MOS devices. The strong effects of the thermal cycle parameters on process uniformity and slips indicate that the overall performance of an RTP tool must be specified both under the steady-state and transient thermal cycles. The electrical characteristics of MOS devices with LRT-grown gate oxides are comparable to those for devices with oxides grown by the trapezoidal thermal cycles.

This paper describes the key process steps in the low temperature, <300ºC, formation of device quality Si/SiO2 interfaces employing oxide deposition by Remote Plasma-Enhanced Chemical Vapor-Deposition (Remote PECVD). The quality of the Si/SiO2 interface correlates with the degree of surface reconstruction that is controlled by ex-situ wet cleaning and in-situ Rapid Flash Heating. Electronic properties of the MOS structure also vary with the deposited oxide thickness, independent of the initial surface quality.

In this paper, we present experimental kinetics data from the literature, and the large discrepancies between them is discussed. An analytical equation for oxide thickness vs. oxidation time and temperature, adequatly describing thin film growth, is used to estimate the temperature error likely to explain the discrepancy between the above data. We also assess this error by considering the temperature sensors.

In this paper we report on the composition of thermally nitrided silicon dioxide films on silicon. Nitridation temperatures ranging from 950 to 1150ºC and nitridation times ranging from 10 to 240 s were used. The purpose of this study is to reveal the mechanisms involved in the nitridation process with emphasis on the role of hydrogen. From the temperature dependence of the amount of nitrogen in the films the effective activation energy for nitrogen incorporation in this initial stage was deduced.

Low pressure chemical vapor deposition of silicon nitride has been studied using a cold-walled, lamp heated, rapid thermal processor. Films were deposited at low presure using both silane and dichlorosilane, diluted in hydrogen and argon carrier gasses. The dichlorosilane and ammonia reaction was found to be unsuitable for use in the cold-walled system. Rapid thermal chemical vapor depositions using silane and ammonia did not result in “bullseye” non-uniformities reported for low presure depositions in conventional hot-walled tube furnaces. Ammonia to silane ratios of 120:1 were found to result in stoichiometric silicon nitride films. Deposition rates are well suited for dielectricapplications. Electrical characteristics are comparable to those of films deposited using APCVD and LPCVD methods.

Ultrathin stacked SiO2/Si3N4/SiO2 films have been fabricated successfully using in-situ multi-step rapid thermal processing chemical vapor deposition (RTP-CVD). Stacked Si3N4/SiO2 (NO) layers were deposited first by RTP-CVD. Some samples were further rapid-thermal oxidized after stacked layer deposition to form oxide/nitride/oxide (ONO) stacked layers. Ellipsometry, Fourier transform infrared spectroscopy (FTIR), x-ray photoelectron spectroscopy (XPS), and Auger electron spectroscopy (AES) were performed to characterize the films. Results show that well defined stacked Si3N4/SiO2 layers were fabricated and for wafers subjected to rapid-thermal oxidation an oxygen-rich SixNyOz layer was formed on the top of the dielectric stack. Nitrogen pile-up at the dielectric/substrate interface was observed for all wafers indicating that nitrogen diffuses into the bottom oxide during nitride deposition even though the deposition temperature is well below those used in thermal nitridation of thermal oxides.

A photoconductive decay curve is analyzed theoretically to determine the surface recombination velocity and the bulk lifetime separately. And it can be applied to experimental photoconductive decay curves using the reflectance microwave probe method. Then it is verified numerically and experimentally to lower the effective surface recombination velocity at p—n and high—low junctions. The high—low junctions used in this study were fabricated from the ionimplanted wafer by rapid thermal annealing or furnace annealing. Then it is shown that the measurement system in relation to surface recombination can apply to evaluations in the ion implantation and its annealing process.

The development of next-generation high-speed bipolar devices depends critically on reproducible shallow dopant profiles, with base and emitter widths considerably less than 1000 Angstroms. Sequential diffusion of boron and arsenic from implanted polysilicon is a promising means of producing such shallow emitter-base profiles. The restricted thermal budget required to reproducibly form such shallow junctions severely limits the use of conventional furnaces. We report the formation of extremely shallow emitter-base profiles using rapid thermal processing (RTP) in a double-diffused polysilicon emitter process. Polysilicon was implanted with various doses of BF2 and subjected to a conventional furnace anneal at 900ºC. This process was followed by As implantation and furnace anneal at 900ºC or RTP at 10500C or 1100ºC. A range of emitter-base profiles was generated with emitter and base widths ranging from 350-800A. Emitter-base profiles were measured using low-energy Secondary Ion Mass Spectrometry (SIMS), after removal of the polysilicon to improve depth resolution. Deconvolution of the instrumental broadening function allowed extraction of base and emitter widths as well as the boron concentration in the base. Variation of the profiles is discussed as a function of anneal times and implant dose. Modified SUPREM III parameters are obtained for diffusivities under these RTP conditions. The implications for high speed bipolar device fabrication will be presented.

The results of a detailed investigation of diffusion of ion implanted As in Si during Rapid Thermal Annealing are reported. A series of experiments has been performed on samples prepared for various thermal treatments, such as peroxidation and preheat. The RTA conditions were chosen at 850°C for 15 seconds in order to study the metastable state. Sample analysis includes depth profiling by RBS and Spreading Resistance measurements, electrical characterization employing Hall measurements, and residual defects by cross-section TEM and planar image. The carrier concentration profile shows the different extent of the mixed Gaussian-Chebyshev polynomial distribution for various prepared samples. We believe the neutral interstitial state I°(Si) survives during RTA for asreceived samples. It gives a Gaussian curve in As profile. The denuded region produced after thermal treatments reduces the oxygen content and creates less 1°(Si) during SPE. So the Gaussian-Chebyshev polynomial distribution was obtained. From the above study, we believe the Gaussian profile can be obtained by controlling RTA conditions This Gaussian-like profile can also suppress hot electron effects by its smooth gradient (generating small electric field) near drain and large overlap under spacer (making large electric field away from gate). So we fabricated rapid thermal annealing singlediffusion drain n-MOSFET. The reduction of hot electron effects was studied, too.

Recent studies have shown that surface metals, introduced by scraping metals either on the silicon wafer front or back surface, can contribute to surface crystalline defects during rapid thermal processing (RTP). These studies have been qualitative in the sense that the quantitative amount of surface metallic contamination was unknown. The work involved here uses Total reflection X-Ray Fluorescence (TXRF) analysis to quantitate the surface metallic contamination on silicon wafers from cleaning (rather than scraping) both before and after RTP. In this study there was no correlation found between surface copper (ranging from 2 to 200 ×1012 atoms/cm2) and surface defects after a RTP of 600°C for 30 seconds in argon, nor was there a correlation between temperature (ranging from 600°C to 1150°C) of the RTP (120 seconds in argon) and surface defects for constant surface copper of about 30×1012 atoms/cm2. The data also revealed the introduction of cross contamination of tungsten to the frontside surface of silicon wafers when air was used as the ambient with an activation energy of 0.8 eV for RTP of 120 seconds in air with temperatures ranging from 500°C to 1000°C. This cross contamination is presumed to come from prior tungsten silicide RTP, even though the quartz tube was etched before this study. Furthermore, the cross contamination of Ga and As occurred to the wafer backsides with no apparent activation energy, and this contamination is presumed to come from prior GaAs annealing several months before.

A detailed comparison between transition metal diffusion results in silicon during rapid thermal annealing obtained in this and other studies with the diffusivity and solubility results obtained in the literature has been made. Using secondary ion mass spectroscopy, U-shaped diffusion profiles, possibly denoting amphoteric diffusion, have been noted fo Cu, Ni, and Pd in silicon during short anneals. Applications are reviewed.

Effects of defect evolution during rapid thermal annealing (RTA) on the anomalous diffusion of ion implanted boron have been studied by implanting silicon ions prior to boron implantation with doses ranging from 1 × 1014cm−2 to 1 × 1016cm−2 at energies ranging from 20 to 150 KeV into silicon wafers. Diffusion of boron atoms implanted into a Si preamorphized layer during RTA is found to be anomalous in nature, and the magnitude of boron displacement depends on the RTA temperature. While RTA of preamorphized samples at 1150°C shows an enhanced boron displacement compared to that in crystalline samples, a reduced displacement is observed in preamorphized samples annealed by RTA at 1000°C. In addition, low dose pre-silicon implantation enhances the anomalous displacement significantly, especially at high RTA temperatures (1 150°C). Finally, the anomalous diffusion is found to depend strongly on the defect evolution during RTA.

Ion bombardment of the surface during CCI2 F2:O2 or C2 H6:H2 :Ar reactive ion etching of GaAs and AlGaAs can produce a heavily disordered near-surface (∼1000A for 380V self-bias on the cathode in a parallel plate reactor) region. The damage in this layer causes carrier depletion effects due to trapping of deep level defects. We have investigated the in-situ and post-RIE annealing of both the structural disorder and the electrical effects of the damage using TEM, ion channelling, C-V and I-V measurements. Etching at 400°C reduced the RIE-induced damage due to dynamic annealing processes. Carrier reductions of approximately an order of magnitude were observed immediately after etching GaAs and AIGaAs in C2H6:H2:Ar; much smaller changes (∼20%) were observed using CCI2F2:O2. For both gas chemistries annealing in the range 200–300°C produced the most ideal I-V characteristics in GaAs, whereas 300–400°C was required for AIGaAs.

Pt/ri low resistance non-alloyed ohmic contacts to p-InP-based contact layers in photonic devices, which were formed by rapid thermal processing (RTP), were studied. E-gun evaporated Pt/Ti metallization deposited onto 1.5· 1019 cm−3 Zn doped In0.53Ga0.47 As yielded the best electrical performance. These contacts were ohmic as deposited with a specific contact resistance value of 3.0 · 10−4 Ωcm2. RTP at higher temperatures led to decrease of the specific contact resistance to 3.4 · 10−8 Ωcm2 (0.08Ωmm) as a result of heating at 450°C for 30 sec. This heat treatment caused only a limited interfacial reaction (about 20 nm thick) between the Ti and the InGaAs, resulted in a thermally stable contact and induced tensile stress of 5.6 · 109 dyne · cm−2 at the metal layer but without degrading the adhesion. Heating at temperatures higher than 500°C resulted in an extensive interaction and degradation of the contact.

Variations of electron traps in molecular-beam-epitaxial (MBE) GaAs layers grown on Si substrates by rapid thermal processing (RTP) have been investigated with deep level transient spectroscopy (DLTS). RTP was performed at 760 – 910 °C for 9s with Si02 encapsulant. In contrast with the layer on GaAs, the traps AI(Ec – 0.65eV) and A2(Ec – 0.81eV) are observed in the layer on Si. The trap EL2h, one of the EL2 family, is produced by RTP in the layer on Si. Some GaAs surfaces were etched to prove the deeper region. In the surface region, the concentrartion of EL2h is comparable to that of EL2 produced by RTP in the layer on GaAs. On the other hand, in ∿ 1 μm below the surface, the concentration of EL2h is about ten times as large as that of EL2. It is speculated that the stress from the GaAs/Si interface enhances the production of the EL2h concentration. In addition to the EL2, the traps R1(Ec – 0.23 eV), R2(Ec – 0.40 eV), R3(Ec – 0.43eV) and R4(Ec – 0.56 eV) are produced by RTP in the GaAs grown on Si.

The spatial distributions of the midgap defect (EL2) concentration in semi-insulating liquid-encapsulated Czochralski GaAs wafers have been characterized by the contactless measurement of the optically injected carrier using reflectance microwave probe (RMP) method. The four-fold symmetrical distribution of EL2 in the (100) plane is observed in the 2 inch diameter GaAs wafer after rapid thermal processing(RTP). The deep level distribution in the RTP wafer corresponds to the crystallographic slip generation pattern obtained from x-ray topography. The correlation between the pattern of the redistributed EL2 concentration and the slip generation in the RTP wafer is suggested that the EL2 is produced by the large thermal stress during RTP. Furthermore, the distributions of EL2 center measured by the RMP method are compared with the dislocation patterns in undoped and In-doped GaAs wafers.

We have studied the effect of an H2 plasma (150 W; 150°C; 10, 20, 50, 100 s) on unannealed and annealed (850°C, AsH3 atmosphere) LEC GaAs material. Using Deep Level Transient Spectroscopy, we have shown that the plasma induces a main bistable defect DO, which has two possible stable states Dl and D2. A complete determination of the corresponding Configuration Coordinate Diagram has been done. Finally, no correlation has been obtained between DO and the native defects EL6, EL3 and EL2. No passivation of the EL2 defect has been observed and the evolution of the D0 concentration results from the association of hydrogen with AsGa. These observations are in disagreement with the identification of EL2 with an isolated AsGa.

Effects of rapid thermal processing (RTP) on SiO2/GaAs interfaces have been studied with X-ray photoelectron spectroscopy, capacitance-voltage measurements and deep-level transient spectroscopy. SiO2 films of 50, 200 and 1250 nim thickness have been deposited on GaAs. RTP has been performed at 760 and 910°C for 9 s. The rapid diffusion of Ga through the SiO2 film occurs, and the As loss and the formation of the As layer near the interface are observed. The decrease of the carrier concentration occurs in all RTP samples. Five electron traps EAI (Ec – 0.27 eV), EA2 (Ec – 0.32 eV), EA3 (Ec – 0.47 eV), EA4 (Ec – 0.58 eV) and EL2 (Ec – 0.78 eV) are produced by RTP. It is considered that the production of the trap EL2 is closely related to the Ga outdiffusion into the SiO2 film and the As indiffusion from the pile-up of elemental As near the interface. Effects of SiO2 film thickness on RTP-SiO2/GaAs are also reported.