The interaction between titanium and nickel silicide films with dislocations generated at the wafer edge by thermal stress is examined in this work. The local dislocation density of the silicon wafers varied from zero to 4.8×106cm across a slice. Both titanium and nickel were deposited as thin films in the contact regions of the p-n junction diodes. Wafers were rapid thermal annealed, sequentially, for 30 s at temperatures between 300°C and 700°C. Reverse bias leakage current measurements of the as-deposited and annealed wafers were used to evaluate the impact of silicides and bulk defects on devices. A significant increase in leakage current due to the silicide/defect interaction was observed above 600 °C for both titanium and nickel. Leakage currents of devices fabricated in regions of high bulk defect density increased with the anneal temperature and dislocation density.

A multicomponent mathematical model incorporating simultaneous Knudsen diffusion and heterogeneous reaction in a feature of arbitrary geometry has been developed to quantitatively predict step coverage in LPCVD. The single component model reveals that for a given CVD chemistry and feature geometry, deposition uniformity is controlled by a single parameter called the step coverage modulus. In multicomponent systems, each additional reactant partial pressure dependence in the deposition rate expression introduces an additional parameter equal to the ratio of the initial reactant partial pressures. Manipulation of the instantaneous step coverage modulus, through time variations of temperature and/or pressure results in higher average film growth rates without incurring a penalty in step coverage over patterned regions of the wafer. For deposition of SiO2 from TEOS, the step coverage modulus is varied through a time dependent temperature path. The path is chosen by constraining the deposition rate in the feature such that it varies by less than a few percent from top to bottom. For deposition of SiO2 from SiH4/O2, silane partial pressure is varied since the reaction rate is relatively insensitive to temperature. In each case. time savings of approximately 50% are achieved.

This paper reports on very shallow double rapid thermally diffused npn transistor junctions, emitter polysilicon sheet resistance, and titanium disilicide formation. A transistor with a 675Å base width fabricated using rapid thermal annealing is demonstrated.

Minority carrier diffusion length measurements (SPV-method) are presented which illustrate the role of contamination, residual impurity content and surfaces in the formation of RTP-induced recombination centers.

A method for producing shallow silicided diodes for MOS devices (with junction depths of about 0.1 µm), by implanting after forming the silicide layer was investigated. The key to this integrated process is the use of rapid thermal annealing (RTA) to activate the dopants in the silicon, so that there is very little thermal broadening of the implant distribution. Self-aligned titanium silicide (TiSi2) films with thicknesses ranging from 40 to 80 nm were grown by RTA of sputter deposited titanium films on silicon substrates. After forming the TiSi2, arsenic and boron were implanted. A second RTA step was used after implantation to activate these dopants. It was found that implanting either dopant caused a sharp increase in the sheet resistivity of the TiSi2. The resistivity can be easily restored to its original value (about 18 µΩ-cm) by a post implant RTA anneal. RBS analysis showed that arsenic diffuses rapidly in the TiSi2 during RTA at temperatures as low as 600°C. SIMS data indicated that boron was not mobile up to temperatures of 900°C, possibly because it forms a compound with the titanium which precipitates in the TiSi 2. Coalescence of TiSi2 occurs during post implant furnace annealing, leading to an increase in the sheet resistivity. The amount of coalescence depends on the film thickness, but not on whether or not the film had been subject to implantation. Spreading resistance profiling data showed that both arsenic and boron diffused into the TiSi2 during furnace annealing, reducing the surface concentrations of dopant at the TiSi2/Si interface. Both N+/P and P+/N diodes formed by this technique exhibited low leakage currents after the second RTA anneal. This is attributed to removal of the implant damage by the RTA. In summary, the second RTA serves the dual purpose of removing implant damage in the TiSi2 and creating the shallow junction by dopant activation.

We have studied stress gradients in thermally grown SiO2 thin films and relaxation of the stress by rapid thermal annealing. These properties were examined by incrementally etching back the SiO2 films and performing infrared spectroscopy and beam-bending measurements at each thickness. The thickness-averaged values measured were then deconvoluted to obtain stress values for thin layers of the SiO2 films. We observed steep stress gradients close to the Si/SiO2 interface for wet oxides which were similar to those previously studied in dry oxides. The stress gradients were steeper for films grown or annealed at high temperatures. In addition, we have been able to show that thin films (= 200 Å) relax more freely than thicker films (= 1000 Å), in which oxide close to the interface is prevented from relaxing by the oxide on top of it.

A manufacturable process must be designed with device integrity and reliability in mind. The optimum cumulative thermal budget should be chosen to achieve a shallow junction (for performance optimization) while minimizing junction leakage. At the same time the processing must satisfy reliability requirements such as good metal step coverage and oxide integrity. Interactions between thermal processes create problems such as repeated anneals, chemical reactions, pattern shifts, and non-equilibrium conditions, as well as opportunities for process simplification, such as greater flexibility in anneal and silicidation processes. In general RTP integration requires a redesign of the complete process sequence.

The TiN/TiSi2 structure, formed by rapid thermal nitridation of a spatter-deposited titanium film, has been demonstrated to be effective as a diffusion barrier and as a low resistance contact material for VLSI submicron metallization. An optimization experiment, designed using the RS/Discover software package, was used to identify a metallization process that minimized p+ resistance as well as maximized barrier capability. Source/drain implant doses, as-deposited titanium film thickness, and rapid thermal processing parameters were the factors varied in the experiment. Of particular significance is a comparison of the effects of a two-step versus one-step rapid thermal anneal on control of the TiN/TiSi2 thickness ratio. A TiN layer of sufficient thickness for barrier integrity and adequate consumption of implant damage in the formation of the TiSi2 layer are desired. Electrical and thermal stability measuremints of the resultant AlSiCu/TiN/TiSi2 p+ contact system are presented.

Epitaxial growth of NiSi2 and CoSi2 on silicon inside miniature oxide openings by rapid thermal annealing has been studied. Effects of lateral confinement, including two-dimensional and linear oxide openings, as well as deposition methods on the growth of NiSi2 and CoSi2 on silicon were investigated. Vast difference found in the behaviors of the growth of epitaxy inside oxide openings between samples with the metal films deposited by electron beam evaporation and sputtering are attributed to the differences in the geometrical configuration of the films and stress levels as well as surface cleanliness.

Thin films of tungsten metal and tungsten silicide were formed by combination of spin-on of tungsten chloride dissolved in a volatile organic solvent, decomposition of the chloride by ion bombardment and finally heating in a new versatile Rapid Thermal Processing (RTP) system. The films resulting from this treatment were characterized by Rutherford Backscattering Spectrometry (RBS) prior to and after the ionic decomposition and heat treatment. The procedure and the results of the analysis are described and discussed in terms of process conditions in this paper.

Stability in the temperature range between 450°C and 525°C of reactively sputter deposited TiN and TiN formed simultaneously with TiSi2 using transient annealing has been investigated in the <Si>/TiSi2/TiN/Al metallization system.

Rapid thermal nitridation (RTN) of metastable Ti silicide in pure ammonia ambient has been shown to result in the formation of a bilayer TiSi 2'TiN structure. This bilayer structure provides an effective self-aligned diffusion barrier against aluminum spiking. Further, the simultaneous formation of TiN on top of the TiSi2 preserves the low resistivity of the silicide layer upon subsequent high temperature process steps. Rutherford backscatttering spectroscopy, Auger electron spectroscopy and four point probe techniques were used to analyze the stoichiometry of the nitrided layer, and to study the kinetics of the nitridation reaction. The nitridation of the metastable silicide film is a substitutional eaction which begins at the surface of the silicide and progresses by substituting nitrogen atoms for silicon. The nitrogen atoms result from dissociation of ammonia The released silicon atoms then diffuse to the silicide'silicon interface and deposit in an epitaxial manner. The benefits of the proposed metallization scheme are substantiated by electrical characterization of the bilayer structure in comparison with a conventional process.

A SALICIDE process is described in this paper, in which ion-beam mixing is used for silicide formation, and doped silicide in conjunction with RTA drive-in are used for shallow silicided junction formation. Fundamental issues related to this process have been investigated, including (i) effects of ion-beam mixing and RTA on the properties of Ti SALICIDE and the interaction between Ti and SiO2; (ii) the self-aligned TiNxOy TiSi2 contact barrier formation and phase transformation; (iii) the mechanism of impurity rediWstrbution and segregation, and junction formation during RTA drive-in; and (iv) the performances and reliability of fabricated SALICIDE devices. Results show that this process may have a great impact on future VLSI technology.

In this paper, the interactions of sputter-deposited Ti on SiO2 substrates during rapid thermal annealing in nitrogen at 550°C - 900°C for 10 - 60 s have been systematically studied using X-ray diffraction, Auger electron spectroscopy, transmission electron diffraction, TEM & cross-sectional TEM, and sheet resistance measurements.

Arsenic out-diffusing from Cobalt Disilicide into underlying silicon displays an enhanced activation level of up to 80%, and an enhanced diffusivity of greater than one order of magnitude. Boron, in contrast, displays a diffusivity as small as 0.25 times that expected. These observations are consistent with a considerable Si-vacancy injection by the silicide layer into the underlying substrate.

It is known that thermal annealing of Ti and amorphous (α) Si first results in an amorphous silicide, after which the crystalline disilicide grows under diffusion control. The situation with respect to the reaction of Ti with crystalline (x) Si is much less clear. We have investigated the reaction of Ti with xSi with (high resolution) cross-section transmission electron microscopy and in-situ Rutherford backscattering spectroscopy. It is shown that an amorphous silicide can also be formed on crystalline Si. The presence of this amorphous silicide as a precursor to the C49TiSi2 phase is suggested to be an important issue in the nucleation and growth of the disilicide.

This paper is based on a detailed study of the effect of high temperature heat treatment in a nitrogen ambient on the titanium silicide film and the silicide-silicon interface. Our investigations showed that the two cannot be studied in isolation. This study involved observing the morphology of the silicide film after thermal treatment in a furnace at 925° C for 5, 30, 60 and 120 minutes. Part of each wafer was then stripped of silicide, thereby exposing the morphology of the interface of TiSi2 with Si. In this way, it was possible to correlate the changes on the surface with that of the interface. The samples were analyzed by scanning electron microscopy and energy dispersive spectroscopy. Evidence for the growth and evolution of Si islands were found as a result of this study. These islands appear to form preferentially at specific locations of the interface, namely at the meeting points of the grain boundaries of the silicide film with the interface. Even though the morphology of the silicide surface becomes more lumpy with increased annealing times, Si islands were not observed at the surface, contrary to what has been reported during vacuum annealing. It appears that the nitrogen ambient has a stabilizing influence in keeping the surface apparently stable. Associated with the increasing size of the islands was the simultaneous sinking of the TiSi2 into the Si substrate.

Electrical characteristics of trench capacitor using RTO oxide, nitroxide and reoxidized nitroxide as the gate insulator are discussed. High temperature RTO is effective to prevent the oxide thinning at the trench corner and dielectric strength of trench capacitor is improved drastically. The lifetime of trench capacitors using RTO is more than 10 times longer than that of trench capacitors using conventional furnaces. Using reoxidized nitroxide as the gate insulator, higher charge to breakdown is obtained. The RTP is superior to the process using the conventional furnace for gate insulator of trench capacitor. Improvement in temperature uniformity and operation reproducibility are essential to RTP equipments for production use.

A new technique of post-oxidation annealing has been introduced to improve the properties and long term reliability of ultrathin (<100 Å) MOS gate dielectrics. In this technique, after oxidation, nitridation is done in NH3 followed by a light reoxidation in O2 and then an inert anneal in Ar or N2. Using this technique both optimum performance as well as reliability can be obtained without sacrificing either. NH3 anneal of SiO2 improved the hot electron immunity, but degraded the interface quality. Good properties could be obtained by a strong reoxidation of the nitrided films, however, at the expense of a substantial increase in the film thickness. Nitrogen and argon ambients were found to be equally effective at improving film properties. By annealing the film in an inert ambient following reoxidation of the nitroxide, fixed charge can be further decreased with little oxide grown, electron mobility in NMOS FETs increases further, and the hot electron lifetime is much longer than that of the starting oxide.

High-quality gate-oxide films for poly-Si TFTs (Thin Film Transistors) are successfully produced by oxygen-argon sputter deposition at a low temperature (200°C). Silicon-oxide films that are sputter-deposited in an oxygen-argon mixture has higher resistivity and breakdown field than films that are sputterdeposited only in argon and thermal oxides grown on poly-Si. Moreover, TFT field-effect mobilities are considerably improved by mixing oxygen into the sputtering gas, resulting in 350 cm2 /V.sec. Subthreshold slope and threshold voltage are also reduced to 5.5 V and 0.8 V/decade. A temperature-dependence measurement of the drain current shows that these improvements in TFT characteristics result from a lowering of the barrier height at the poly-Si grain boundaries, indicating a reduction in the trap density at these boundaries. Results confirm the usefulness of gate-oxide films that are sputter-deposited in an oxygen-argon mixture, for lowtemperature fabricated poly-Si TFTs.