DLTS has been used to investigate deep level defects induced by Pulsed Electron Beam Annealing (PEBA) in virgin (100) boron doped silicon. Various PEBA conditions were selected resulting in different molten layer thicknesses, melt front velocities and thermal gradient distributions. Discrete hole traps distributed in the regrowth layer were observed in all the annealed samples. The activation energies and thermal signatures of these levels do not correspond to already known defects except for one level which has been assigned to the carbon interstitial substitutional pair. Carbon contamination during irradiation is the most probable explanation for the creation of this defect. Other discrete hole trap levels are likely to be generated by quenching of the molten layer as far as their profiles do not extend beyond the regrowth layer. Moreover, a broad band of levels, characteristic of extended defects, has been observed only on the samples which have suffererd the highest thermal stresses. This band of levels might be related to the generation of dislocation networks as recently observed by means of T.E.M. on the same PEBA processed samples.

Regrowth by pulsed proton beam was studied for evaporated amorphous Si layers, for layers converted to polycrystalline by annealing (both with and without Ge markers) and for implantation-amorphized SOS films. Silicon-on-sapphire showed the lowest threshold for regrowth. Amorphous silicon melted at about 0.2 J/cm2 lower fluences of protons of 380 kev energy than crystalline Si. Implanted Sb into Sos occupies lattice positions exceeding the solid solubility.

A scanning arc lamp annealing system has been built using a 3” long mercury arc lamp with an elliptical reflector. The reflector focuses the light into a high intensity narrow line source. Silicon wafers implanted with 100 Kev 75As+ to 1×l015 cm−2 have been uniformly annealed with a single scan, resulting in complete activation and negligible redistribution of the implanted species. Using a scan rate of 1cm/s, entire 3” wafers have been annealed in less than 10 seconds with this system. The system has also been used to recrystallize thin films of polysilicon deposited on thermally grown silicon dioxide. The recrystallized films contain grains that are typically 0.5–1 mm in width and several centimeters long. Surface texture measurements show the crystallites to be almost entirely (100) in the plane of the film with the orthogonal <100>direction closely paralleling the scan direction. Mosfets were fabricated in these films with surface mobilities 66% of ones fabricated in single crystal silicon. An epitaxial layer with the same crystallographic features as the recrystallized film was grown on the film itself.

The use of zone melting recrystallization (ZMR) to prepare large-grain(and in some cases single-crystal) semiconductor films is reviewed, with emphasis on recent work on Si on SiO2. Encapsulants are generally required to minimize contamination and decomposition, induce a crystalline texture,improve surface morphology and prevent agglomeration. In the case of Si, the solid-liquid interface is faceted, which gives rise to subboundaries. These can be entrained by laterally modulating the temperature through the use of an optical absorber on top of the encapsulant. Control of thermal gradients and in-plane crystallographic orientation are important for reliable entrainment.

Electronic defects in strip-heater crystallized silicon thin films have been investigated with capacitance-voltage (C-V),deep-level spectroscopic, and scanning-electron microscopic techniques. For electrical characterization the crystallized silicon films were used to fabricate inverted metal-oxide-silicon capacitors in which degenerately doped bulk silicon substrates provided the gate electrode. High-frequency C-V characteristics yield effective fixed-charge densities in the oxide of ≤ 2×1011 cm−2. Trap-emission spectra, recorded with deep-level transient spectroscopy on both p-type and n-type capacitors, indicate a continuous distribution of deep levels throughout the silicon bandgap. The Si-SiO2 interface is considered to be the principal source of this deep-level continuum, since the films are essentially single crystal with a low density of subgrain boundaries; the effective interface-state density is ≤ 2.5×1010 eV−1 cm−2. A discrete energy level, detectable above the background continuum,appears in the upper half of the silicon bandgap; it may identify a point defect in the bulk of the silicon film with a spatially uniform density of approximately 1×1013 cm−3. On lateral p-n junction diodes, electron-beam-induced-current images reveal enhanced diffusion of arsenic along structural defects intersecting the junction.

Electrical and crystal properties of seeded lateral epitaxial Si are evaluated as a function of distance from seeding area with the aid of a micro-probe RHEED and MOSFET fabrication. the results indicate that the quality of a grown layer is as good as that of bulk Si Crystal for most of the epitaxial layer. However, at the SiO2 edge, electrial properties are somewhat poor due to the existence of dislocation and residual stress.Element devices useful for SO structures are fabricated. Electrical properties of MOSPET's with double active areas indicate that surface and bottomregions of the epitaxial layer are all of device worthy quality.Insulated control gate bipolar type transistors are proposed and some preliminary results are shown.

The incorporation of nitrogen and oxygen in polysilicon has been examined by SIMS. The analysis, combined with C-V measurements and ion implantation, has been used to correlate the incorporation of the two species with the fixedcharge density at the back polysilicon/Si02 interface. Laser recrystallization with a silicon-nitride encapsulation layer results in the inclusion of 2–4 × 1017 cm−3 nitrogen atoms in the polysilicon; if an oxide capping layer is used, the nitrogen level observed is at the background of the SIMS system (~1015cm−3). Either type of capping layer results in 3−4×1018cm−3 oxygen atoms being incorporated into the polysilicon. Implantation of nitrogen into the polysilicon before recrystallization increases the fixed-charge density Nf,b) at the back interface, while implanted oxygen decreases Nf, b. The high Nf, b found with a nitride capping layer is attributed to deposition of nitrogen or SiNx at the back interface.

CW laser annealing has been performed on silicon on sapphire (SOS) implanted with boron or phosphorus ions to a dose of 1015 ions/cm2 . The laser irradiation was done both with and without an oxide layer on top of the silicon and from both the silicon and the sapphire side. Sheet resistivity and Hall effect measurements were used for the analysis of the samples. Good annealing and high activation of the dopants were obtained for both oxidized and unoxidized SOS. For samples irradiated from the silicon side, the needed laser power changed depending on the thickness of the oxide. For samples irradiated from the sapphire side, the needed laser power was independent of oxide thickness.

A shaped laser beam has been used for laterally seeded recrystallization of polysilicon films over oxide. Direct maps of the shaped-beam intensity distribution in the wafer plane are correlated with the grain structure of the recrystallized polysilicon. Using 60% overlapping of shaped-beam scans along <100> directions, we have obtained seeded areas one mm wide and 50 to 500μm long. These consist of 40μm-wide adjacent single-crystal strips regularly separated by low-angle grain boundaries extending laterally away from the seed openings. The spacing between grain boundaries is equal to the scan spacing, providing a means for controlling the location of grain boundaries in otherwise defect-free, single-crystal films.

A thermal model for beam-induced melting of polysilicon in polysilicon/insulator/silicon structures has been used to compare CW Ar+ laser and electron-beam melting processes. The laser melting process exhibits a decreasing recrystallization threshold power and an increasing substrate melting threshold power with increasing insulator thickness. The decrease in recrystallization threshold with increasing insulator thickness is generally smaller for electron beams because of their deep penetration. The substrate melting threshold is approximately independent of insulator thickness for e-beams since no change in the power absorption occurs on melting of the polysilicon. As a result, the process window between the onset of recrystallization and melting of the substrate is narrower for e-beams than for laser beams. Also, essentially no window will exist between the onset of melting over a seed and substrate melting under an oxide if lateral epitaxy is performed with an electron beam.

In this paper we review the current understanding of laser-induced silicon thin film crystal growth on bulk amorphous substrates. We propose a model for oriented nucleation and show that the silicon reflectivity jump on melting coupled with radiant heating lead naturally to this autonucleation mechanism. We then survey various techniques for control of lateral epitaxial growth and conclude with the results of some recent electrical device characterization.

Selective absorption, using patterned dielectric films, and beam shaping were used as means for improving the recrystallization of LPCVD polysilicon islands on fused quartz. IR imaging of the laser heated region was used to optimize and control the recrystallization. MOSFETs were fabricated in laser-recrystallized silicon islands on amorphous substrates using a standard n-channel poly-gate process. Devices with various channel lengths and widths were fabricated, and the dependence of threshold voltage, channel mobility, and leakage on recrystallization conditions and device dimensions was studied.

A swept line-source electron beam has been used to study unseeded Si-on-insulator crystallization at beam scan speeds of 150–1500 cm/s. For a particular sample configuration a maximum linear crystallization velocity of ~ 350 cm/s was observed. At higher sweep speeds, competing nucleation occurred at intervals across the film. Both the limit in crystallization velocity and the intervals between nucleation are tentatively explained by a simple model.

This paper describes the production of large areas of precisely oriented, defect-free, single crystal silicon films on SiO2 by dual electron beam heating of deposited polysilicon using lateral epitaxy. Defects which occur in the film far from the seeding window are characterised, and the dependence of the area of the defect-free region on the processing conditions is discussed.

Incoherent tungsten radiation has been used to recrystallize polysilicon films deposited on SiO2, grown on 75 mm diameter wafers. These films have been analyzed by a variety of techniques such as optical microscopy, Auger spectroscopy and TEM crosssectioning. These films are large (> 50 mm dia.) single crystals, and contain fewer defects and impurities than similar films recrystallized in graphite strip heater ovens. They do, however, contain the subgrain boundaries found previously, even when high purity Mbe polysilicon is used. In vertical tem cross-sectioning, in addition to the subgrain boundaries,we have seen crystallized particles of 50200 Å size in the si film at both the upper and lower SiO 2 boundaries. Although these particles could be relatedto formation of the subgrain boundaries, no definite correlation has been made.

Recently we reported the first successful crystallization from the melt of 15,μm thic Si films on SiO2. In this technique of Lateral Epitaxial Growth over Oxide (LEGO), crystallization is initiated at seeding vias in SiO2 and propagates over the amorphous insulator, resulting in high structural quality of the grown film. Uniform and bow-free crystallization of complete 3-inch wafers occurs in <60 sec in a special furnace, with wafers placed between a bank of high intensity tungsten halogen lamps and a water cooled base.

In this paper we provide further details of crystallization procedure and new structural characterization data. The mechanism of LEGO crystallization and its limitations are also discussed.

The lure of flat panel displays has stimulated much research on the crystallization of silicon films deposited on large-area transparent substrates. In most respects, fused quartz is ideal. It has high purity, thermal shock resistance, and a softening point above the silicon melting temperature. Unfortunately, fused quartz has such a small thermal expansion that the silicon film cracks as it cools. This problem has been attacked by patterning with islands or moats before and after crystallization, by capping, and by using silicate glass substrates that match the thermal expansion of silicon. The relative merits of these methods are compared. Melting of the silicon film to achieve high mobility has been accomplished by a variety of methods including lasers, electron beams, and strip heaters. For low melting temperature glasses, surface heating with a laser or electron beam is essential. Larger grains are obtained with the high bias temperature, strip heater techniques The low-angle grain boundaries characteristic of these films may be caused by constitutional undercooling. A model is developed to predict the boundary spacing as a function of scan rate and temperature gradient.

Device-quality Si films have been prepared by using graphite strip heaters for zone melting poly-Si films deposited on SiO2-coated substrates. The electrical characteristics of these films have been studied by the fabrication and evaluation of thin-film resistors, Mosfets and MOS capacitors. High yields of functional transistor arrays and ring oscillators with promising speed performance have been obtained for CMOS test circuit chips fabricated in recrystallized Si films on 2-inch-diameter Si wafers. Dualgate Mosfets with a three-dimensional structure have been fabricated by using the zone-melting recrystallization technique.

Thin-film transistors (TFT) have been fabricated in scanned CO2 laser-crystallized silicon films on bulk fused silica. In n-channel enhancement-mode transistors, it is demonstrated that an excessively large leakage current can be electric-field modulated with a gate electrode located beneath the silicon layer. This dual-gate configuration provides direct verification on bulk glass substrates of back-channel leakage as has recently been demonstrated for beam-crystallized silicon films on thermal oxides over silicon wafers. With the application of deep-channel ion implantation to suppress back-channel leakage, high-peformance TFTs have been fabricated in single-crystal silicon films on fused silica. The results demonstrate that scanned CO 2 laser processing of silicon films on bulk glass can provide the basis for a silicon-on-insulator technology.

We present a model based on analytic solutions to the heat equation that calculates the temperature profiles induced by line shaped heat sources. The sensitivity of isotherms to various heating conditions including the effect of tailoring power profiles in both curved and straight sources is discussed. Conditions are presented that result in “dogboned” shaped isotherms. Also shown is the effect that inhomogeneities (e.g., power density fluctuations or defects in the material have on the ideal temperature profiles.