We focused on detailed evaluations of properties of the ultra-thin pore-seal layer (< 3 nm-thick), such as Cu diffusion barrier property and thermal stability. Cu diffusion into dense thermal silica and porous silica low-k which are covered with the pore seal layer was evaluated using metal-insulator-semiconductor (MIS) capacitors under bias thermal stress (BTS). Triangular voltage sweep (TVS) measurement shows that the ultra-thin layer on dense thermal silica suppresses the drift of Cu ions. The Time-Dependent Dielectric Breakdown (TDDB) lifetime of porous silica low-k covered with the ultra-thin pore seal layer results in a drastic increase of the capacitor lifetime with respect to the no-pore-seal control system (stable at 125 °C at least for 10000 s). Thermal decomposition of bulk material of the pore sealant was measured by thermal gravity (TG) test in nitrogen. Bulk material did not decompose through around 350 °C. The amount of ultra-thin pore seal layer fabricated on silicon wafer after thermal cycle stress in vacuum was measured by x-ray photoelectron spectroscopy (XPS). Amount of pore sealant did not decrease even after 2 cycles of 20 min, at 250 °C. Those results show that the ultra-thin layer, which we propose here, has a potential as a pore seal layer for porous low-k films.

A new organic precursor was designed and synthesized in order to form polymer films having low dielectric constants by a plasma-enhanced co-polymerization (PCP) technology. The organic monomer features a large aliphatic hydrocarbon structure, tricyclodecane (TCD) group. Optimized polymer films deposited from the monomer had dielectric constants less than 2.5. A solid 13C-NMR spectrum showed that the TCD moiety in the precursor was included in the polymer without changing the structure. The effect of the deposition temperature on the film structure was studied by analyzing Raman spectra. It was revealed that the dielectric constant is strongly associated with sp2 carbon content in the TCD-based polymer films.

A novel process of TMCTS vapor annealing combined with a plasma treatment has been developed for improving the mechanical strength of porous silica films having ultralow dielectric constant. When porous silica films annealed under 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS) vapor were treated with argon plasma and then re-treated with TMCTS vapor, the mechanical strength (i.e., elastic modulus, hardness) of the films increased significantly. Results of Fourier transform infrared spectroscopy (FT-IR) suggested an accelerative effect resulted from the plasma treatment on the conversion of Si-CH3 and Si-H groups to Si-OH groups. The latter group appears to react faster with TMCTS from the second annealing to form cross-linked polymer network on the porous silica wall surfaces. The resulting cross-linked network is thought to keep the low permittivity and enhance the mechanical strength of the low-k films.

Periodic 2-dimensional (2-D) hexagonal and the disordered pore structure silica films have been developed using nonionic surfactants as the templates. The pore structure was controlled by the static electrical interaction between the micelle of the surfactant and the silica oligomer. No X-ray diffraction peaks were observed for the disordered mesoporous silica films, while the pore diameters of 2.0-4.0 nm could be measured by small angle X-ray scattering spectroscopy. By comparing the properties of the 2-D hexagonal and the disordered porous silica films which have the same porosity, it is found that the disordered porous silica film has advantages in terms of the dielectric constant and Young's modulus as well as the hardness. The disordered porous silica film is more suitable for the interlayer dielectrics for ULSI.

A novel organosiloxane-vapor-annealing method has been developed for improving the mechanical strength of porous silica films with a low dielectric constant. Treatment of a porous silica film with 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS) under atmospheric nitrogen above 350 °C significantly enhanced the mechanical strength (i.e., elastic modulus and hardness) of the film. Results of Fourier transform infrared spectroscopy (FT-IR) and thermal desorption spectroscopy (TDS) suggested the formation of cross-linked poly(TMCTS) network on the porous silica internal wall surfaces by the TMCTS treatment. Such TMCTS cross-linked network is thought to enhance the mechanical strength of the low-k film.

The evidence of copper (Cu) ion drift in low-dielectric-constant (low-k) interlayer films is clearly shown by transient capacitance measurements for the first time. The bias-temperaturestress (BTS) was applied to the copper electrode of Cu/low-k/p-Si metal-insulator-semiconductor capacitors. After injecting photoelectrons into the low-k film from the substrate, time-dependence of the capacitance was measured. When BTS-applied samples were measured, a decrement of the capacitance was observed, whereas not observed without BTS. The decrement of the capacitance was attributed to thermal emission of electrons from copper-related electronic states. By assuming an attempt-to-escape frequency of the charge from the electronic states, the energy level of Cu was estimated to be 0.8–0.9 eV below the conduction band edge.

We have recently developed novel periodic nanoporous silicate glass with high structural stability as low-k thin film by spin-coating method. Periodic porous silicate glass films developed so far cause structural shrinkage (10>∼20% or more) by annealing the spin-coated films. In this investigation we adopt vapor-phase TEOS (tetraethoxysilane)-treatment before anneal. Our novel nanoporous film shows little shift of XRD peak position after annealed at 673K, indicating both the ultimate mechanical strength and the minimization of stress in the interface between the prepared film and the underlying substrate. Such a shrinkage-free periodic nanoporous silica film can possess higher VBD (break down voltage) and lower ILeak (leakage current). In this article we estimate structural properties (including information on pores introduced intentionally) by XRD and TEM observation, and electrical properties (dielectric constant, VBD and ILeak) by IV and CV measurement of this special-treated periodic nanoporous silica film. The dielectric constant of the thus prepared periodic porous silica film with silylation after calcination was evaluated to be around 1.8 at 100kHz.

This paper describes silicide and salicide technologies in Japan for 0.35 μm CMOS ULSIs and beyond. Polycide gate electrodes have been developed for CMOS devices from 1.0 μm to 0.35 μm design rule regime, in which Wsi2 has been used dominantly as a silicide gate material. On the other hand, silicide films are formed selectively on source/drain diffusion layers by salicide techniques, in which TiSi2 is used as a salicide material. TiSi2 is also used as a salicide material of both gate electrodes and source/drain diffusion layers for dual gate (n+/p+) CMOS. The TiSi2 thin film is formed by Ti sputtering and subsequent rapid thermal annealing. A preamorphization technique before Ti sputtering has been developed to obtain equal silicide properties on p+ and n+ diffusion layers. A high-temperature Ti sputtering technique has been developed in conjunction with pre-amorphization. CoSi2 and NiSi have also been developed as salicide materials for quartermicron CMOS and beyond.

A polycrystalline-silicon surface with hemispherical-grain (HSG) is deposited by low-pressure chemical vapor deposition at the transition temperature of the film structure from amorphous to polycrystalline. The surface area of the HSG-Si film is about twice as large as Si films deposited at other temperatures. It is found that the HSG-Si is not formed during deposition, but formed during annealing of amorphous Si surface after deposition. At the annealing temperature which is maintained to be the transition temperature, HSG-Si is formed by the nuclei generation on the amorphous-Si surface and the outward crystalline growth of grains dixough migration of surface Si atoms. By applying the HSG-Si film as the storage electrode for a 64Mbit dynamic random access memory (DRAM) stacked-capacitor with a SiO2Si3N4 dielectric film, twice the capacitance is obtained. The increase in the capacitance makes it possible to reduce the DRAM cell area, even by using a relatively thick dielectric film for higher reliability. Consequently, the HSG-Si technique is applicable to the fabrication process for 64Mbit and larger DRAMs.