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0.35 μm Technologies in Japan

Published online by Cambridge University Press:  15 February 2011

Takamaro Kikkawa  and
Isami Sakai
Takamaro Kikkawa
Affiliation:
ULSI Device Development Laboratories, NEC Corporation 1120 Shimokuzawa, Sagamihara City, 229 Japan
Isami Sakai
Affiliation:
ULSI Device Development Laboratories, NEC Corporation 1120 Shimokuzawa, Sagamihara City, 229 Japan
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Abstract

This paper describes silicide and salicide technologies in Japan for 0.35 μm CMOS ULSIs and beyond. Polycide gate electrodes have been developed for CMOS devices from 1.0 μm to 0.35 μm design rule regime, in which Wsi2 has been used dominantly as a silicide gate material. On the other hand, silicide films are formed selectively on source/drain diffusion layers by salicide techniques, in which TiSi2 is used as a salicide material. TiSi2 is also used as a salicide material of both gate electrodes and source/drain diffusion layers for dual gate (n+/p+) CMOS. The TiSi2 thin film is formed by Ti sputtering and subsequent rapid thermal annealing. A preamorphization technique before Ti sputtering has been developed to obtain equal silicide properties on p+ and n+ diffusion layers. A high-temperature Ti sputtering technique has been developed in conjunction with pre-amorphization. CoSi2 and NiSi have also been developed as salicide materials for quartermicron CMOS and beyond.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 402: Symposium H – Silicide Thin Films-Fabrication, Properties and Applications , 1995 , 199
Copyright
Copyright © Materials Research Society 1996

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