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Hf and Zr incorporation from thermally annealed high-κ gate dielectric thin films (4-5 nm) candidates HfSixOy and ZrSixOy into Si are presented. The dielectric films were subjected either to rapid thermal annealing (RTA) or standard furnace annealing in an N2 atmosphere. After annealing, the films were removed by chemical etching prior to depth profiling using both time of flight secondary ion mass spectroscopy (ToF-SIMS), and Heavy Ion Rutherford Backscattering Spectrometry (HI-RBS) combined with UV-ozone oxidation/etching cycles. As-deposited and annealed films were studied using monochromatic X-ray Photoelectron Spectroscopy (XPS), and high resolution TEM. A Zr incorporation depth after annealing of up to 20 nm into the Si substrate was observed. Depth profiling shows that, although most of the remnant Zr after annealing/etching is located at or near the surface of the Si substrate, incorporation into the substrate is also present. No significant Hf diffusion into Si was observed for either RTP or furnace-annealed films
Nano-ZnS was deposited into porous silicon. By varying the concentration of Zn2+ ion solution during nano-ZnS formation, the amount of nano-ZnS in porous silicon host can be controlled. The doped porous silicon exhibited a gradual shift in its photoluminescence peak from red to blue as a function of the nano-ZnS coverage. At an optimum doping, white light photoluminescence was obtained. A study in the luminescence lifetime showed that the radiative recombination at the blue end of the visible spectrum was due to nano-ZnS, whereas, luminescence emission at the red end of the visible spectrum came from porous silicon. The latter luminescence was due to in part tunneling of excited electrons from nanoZnS into porous silicon and in part direct excitation of porous silicon layer. Time-resolved photoluminescence also showed that radiative recombination was effectively dominated by the nano-ZnS. Photoluminescence excitation result revealed the presence of two excitation levels; one belonged to nano-ZnS at near uv region, and another at about 520 nm from the surface states of porous silicon and nano-ZnS. The doping of nano-ZnS into porous silicon demonstrates that luminescence color tuning is possible when an appropriate functional material is introduced into porous silicon.
A model is presented that describes silicon nanoparticle deposition in terms of disilane decomposition on silicon dioxide, adatom diffusion, nucleation, nanoparticle growth and coalescence. Total nanoparticle densities are output as a function of time, and segregation of nanoparticles into subsets with common size allows size distributions to be reported for all times during the simulation. Model parameters are fit to low pressure chemical vapor deposition data with disilane pressures ranging from 5×10−4 to 5×10−3 Torr and surface temperatures from 510 to 570 °C. Simulations are used to explain how growth pressure and surface temperature influence incubation time, nanoparticle density and size distribution.
Strain relaxation in He+-implanted and annealed Si(001)/Si1−xGex heterostructures was investigated using transmission electron microscopy techniques and x-ray diffraction. Depending on the implant conditions, bubbles and/or platelets form below the Si/Si1−xGex interface upon annealing and act as nucleation sources for dislocation loops. The dislocation loops extend to the interface and form a misfit dislocation network there, resulting in relaxation of 30-80% of the strain in layers as thin as 100-300 nm. When bubbles form close to the interface, dislocations nucleate by a climb loop mechanism. When smaller bubbles form deeper in the Si substrate an irregular three-dimensional dislocation network forms below the interface resulting in an irregular misfit dislocation network at the interface. When platelets form deeper in the Si substrate, prismatic punching of dislocation loops is observed and dislocation reactions of misfit dislocations at the interface result in Lomer dislocation formation.
Effects of process annealing temperature on Metal-Induced-Lateral-Crystallization (MILC) growth rate and quality of MILC polysilicon formed were studied. Raman spectrum analysis was employed for material characterization. MILC polysilicon layer, which was formed by applying an optimum annealing condition together with post high temperature annealing, could be used to fabricate Thin-Film-Transistor (TFT) with considerably electrical improvements. This reflected that good quality of the polysilicon layer. It is believed that the proposed MILC formation method can be empolyed to produce large grain polysilicon on insulator (LPSOI) for advanced devices and circuits' fabrication.
Strained-Si MOSFET is an attractive device structure to be able to relax several fundamental limitations of CMOS scaling, because of high electron and hole mobility and compatibility with Si CMOS standard processing. In this paper, we present a new device structure including strained-Si channel, strained-SOI MOSFET, applicable to CMOS under sub-100 nm technology nodes. The main feature of this device is that thin strained-Si channel/relaxed SiGe hetero-structures are formed on buried oxides. The principle and the advantages are described in detail. The strained-SOI MOSFETs, whose electron and hole mobility is 1.6 and 1.3 times, respectively, higher than in conventional MOSFETs, have successfully been fabricated by combining the SIMOX technology with re-growth of strained Si films. We also present novel fabrication techniques to realize ultra-thin SiGe-on-Insulator (SGOI) virtual substrates with high Ge content, including Ge condensation due to oxidation of SGOI with lower Ge content. Strained-Si/SGOI structures with total thickness of 21 nm and Ge content of 56 % have been fabricated by oxidizing SiGe films on conventional SOI substrates and re-growing strained-Si films.
Capacitance-Voltage (C-V) hysteresis was observed in the Metal-Oxide-Semiconductor (MOS) capacitor with silicon nanocrystals. The MOS capacitor was fabricated by thermal oxidation of Si nanocrystals, which were deposited on an ultra-thin thermal oxide grown previously on a p-type Si substrate. The Si nanocrystals were deposited by the gas evaporation technique with a supersonic jet nozzle. The size uniformity and the crystallinity of the Si nanocrystals are found to be better than those fabricated by the conventional gas evaporation technique. The C-V hysteresis in the MOS capacitor is attributed to electron charging and discharging of the nanocrystals by direct tunneling though the ultra-thin oxide between the nanocrystals and the substrate. The flat-band voltage shift observed during the C-V measurement depends on the size and density of the nanocrystals and also on the magnitude of the positive gate bias for charging. The retention characteristic is also discussed.
The diffusion behavior of ion implanted arsenic and phosphorus in relaxed-Si0.8Ge0.2 is investigated. Both dopants exhibit enhanced diffusivities in SiGe compared to those in Si under equilibrium conditions. The ratio of the effective diffusivity in SiGe relative to that in Si is found to be approximately seven for arsenic, and roughly two for phosphorus at high concentrations. Under transient diffusion conditions, arsenic diffusion in SiGe is retarded while arsenic diffusion in Si is enhanced by the ion implant damage. The transient retardation of arsenic diffusion in SiGe is observed at temperatures ranging from 900 to 1050°C. These results suggest that using arsenic, it is possible to form n+/p junctions in relaxed-Si0.8Ge0.2 as shallow as those in Si, by optimizing the implant annealing conditions.
A technique to form metal nanocrystals on silicon or thin SiO2 film by Rapid Thermal Annealing (RTA) of thin metal film is developed and integrated into standard CMOS processing to make EEPROM devices and improve metal-semiconductor contact resistance. I-V and C-V measurements are carried out on MOSFETs and MOS capacitors containing Au, Ag, Pt, and Si nanocrystals as floating gate for universal mobility and minority carrier lifetime extraction. Mobility around 300 cm2/V-sec and minority carrier lifetime within 0.02 ∼ 0.1 μsec are observed for all cases including the control samples that do not go through the metal nanocrystal formation process, which suggests that the substrate is virtually free from metal contamination. Using this technique, thicker metal film can potentially be achieved as well by stitching thin metal layers on top of the nanocrystals.
A new self-assembly patterning method for generation of epitaxial CoSi2 nanostructures was used to fabricate 70 nm gate-length Schottky barrier metal oxide semiconductor field effect transistors (SBMOSFETs) on silicon-on-insulator (SOI) substrates. This technique involves only conventional optical lithography and standard silicon processing steps. It is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal processing. The strain field is generated along the edges of a mask consisting of 20 nm SiO2 and 300 nm Si3N4. Single-crystalline CoSi2 layers grown by molecular beam allotaxy (MBA) on thin SOI substrates were patterned using this technique. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. During the RTON-step a 6 nm thin SiO2 is formed on top of the gap which is used as a gate oxide. The SBMOSFETs can be driven as both p-channel and n-channel devices without complementary substrate doping and show good I-V characteristics.
The thermal stability of strained Si on relaxed Si1−xGex structures annealed at 1000 °C was investigated using high-resolution x-ray diffraction, Raman spectroscopy and transmission electron microscopy. Interdiffusion at the Si/Si1−xGex interface is negligible for annealing times <30 sec and is independent of the initial Si layer thickness and the composition of the Si1−xGex layer. In all cases the Si layers remained nearly fully strained, but a significant density of misfit dislocations was seen in layers that exceeded the critical thickness for dislocation glide. The Si layer thickness could be measured for layers as thin as 7 nm.
Micro-Raman spectroscopic investigations of arsenic-implanted silicon show lines characteristic of silicon crystallites even at implant doses above the amorphization threshold. The intensity and frequency of occurrence of the lines increase with the implanted dose. Polarization/orientation Raman studies indicate the crystallites are silicon in the hexagonal phase (Si-IV) and silicon in the diamond phase (Si-I). The latter are oriented differently than the substrate silicon. Monte Carlo simulations of the arsenic ion energy loss and published molecular dynamics studies suggest that each arsenic ion deposits sufficient energy to locally melt the silicon lattice. This is taken as the basis of the present attempt to explain the origin of the crystallites. A one-dimensional numerical model is developed to determine the time scale for the liquid silicon to solidify. The effect of amorphous silicon on the solidification is also investigated.
High-quality short-period Si/SiGe strained-layer superlattices have been grown on bulk single-crystal SiGe substrates using a commercial low-temperature ultrahigh vacuum chemical vapor deposition (UHV/CVD) reactor. These superlattices were characterized by high-resolution x-ray diffraction (HRXRD), Auger electron spectroscopy (AES), atomic force microscopy (AFM), cross-sectional transmission electron microscopy (XTEM) and photoluminescence (PL). HRXRD, AES, and XTEM results confirm that the materials deposited are high crystal-quality superlattice layers with abrupt interfaces and excellent thickness and composition uniformity across superlattices of 5 periods. AFM images show similar surface RMS roughness of much less than 1 nm for both the top layer surface and the starting substrate surface, indicating very smooth surfaces. PL measurements further confirm material quality and composition, and show sharp, well-resolved near band-edge BE and FE PL and strong broad sub-gap PL perhaps related to direct-gap superlattice transitions. The materials grown here are very promising for applications of both high-speed electronic devices and high-efficiency optoelectronic devices.
In this work, local AFM oxidation technique in a controlled humidity environment has been used to create small features in strained SiGe alloys. When directly oxidizing SiGe alloys, minimum line widths of 20nm were achieved by adjusting parameters such as the bias voltage on the microscope tip and the tip writing speed. It was found that when bias voltage increases, and/or when the tip writing speed decreases, the oxidation height of silicon-germanium increases. In contrast to conventional thermal oxidation, the oxide height on SiGe alloys is slightly less than that on Si. Finally, this method was used to successfully cut conducting SiGe quantum well lines with high resolution.
We prepared a SiO2/nanocrystalline Si (nc-Si)/SiO2 sandwich structure. A clear positive shift in C-V and G-V curves due to electrons trapped in nc-Si dots has been observed at room temperature. The peak in conductance around flat band condition indicates that a trap event had occurred where an electron is stored per nc-Si dot. A logarithmic charge loss function is found and this discharging process is independent of the thermal activation mechanism. The longer memory retention time and logarithmic charge loss in the dots are explained by a “built-in” electric field through the tunnel oxide, which varies with time, resulting in a variable tunneling probability. The electric repulsion induced by the built-in electric field hinders the discharging of electrons remained in the dots.
Polycrystalline diamond films previously grown on silicon were polished to an RMS roughness of 15 nm and bonded to the silicon in a dedicated ultrahigh vacuum bonding chamber. Successful bonding under a uniaxial mechanical stress of 32 MPa was observed at temperatures as low as 950°C. Scanning acoustic microscopy indicated complete bonding at fusion temperatures above 1150°C. Cross-sectional transmission electron microscopy later revealed a 30 nm thick intermediate amorphous layer consisting of silicon, carbon and oxygen.
In this study, the initial growth characteristics of a SiGe film realized by ultrahigh-vacuum chemical vapor deposition (UHV CVD) using GeH4 and Si2H6 on high-K gate oxide, ZrO2, has been investigated in the temperature range from 475°C to 550°C. The influence of surface reactions on growth characteristics such as the incubation of growth, roughness of the SiGe layer, and the interface reaction of the SiGe film with ZrO2were studied using atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM). From our analysis we conclude that ZrO2 reacts with Si and forms zirconium silicide in the temperature range between 500°C and 550°C. The surface roughness of amorphous SiGe layers increase from 0.5nm to 1.5nm by increasing Ge content from 0.1 to 0.3. A further increase of surface roughness is observed from less than 1nm to 5nm as SiGe layer transitions from an amorphous to a poly crystalline layer.
Device modeling data and some early experiments suggests that fully depleted MOSFET devices where channel is controlled by two opposing gates or one gate that surrounds most or the entire channel, will provide better scaling than the classic devices with one gate on one side of the channel. However, formation of such devices requires complex, non-conventional and sometimes exotic geometry and processing, ranging from wafer bonding to selective lateral ‘tunnel’ epitaxy, to selectively wet-etched channels with triangular cross-section. Classic single-gate transistors have been recently demonstrated with reasonable performance at 20-15 nm of physical gate length. Double-gate transistors with their process integration complexity will likely become a viable alternative for smaller geometries. This paper will discuss various approaches to realization of those multi-gate fully depleted devices and their process integration challenges for sub-15 nm gates.
We have fabricated strained Ge channel p-type metal oxide semiconductor field-effect transistors (p-MOSFETs) on Si1−xGex (x=0.7 to 0.9) virtual substrates. Capping the channel with a relaxed, epitaxial silicon layer eliminates the poor interface between silicon dioxide (SiO2) and pure Ge. The effects of the Si cap thickness, the strain in the Ge channel, and the thickness of the Ge channel on hole mobility enhancement were investigated. Optimized strained Ge p-MOSFETs show hole mobility enhancements of nearly 8 times that of co-processed bulk Si devices across a wide range of vertical field. These devices demonstrate that the high mobility holes in strained Ge can be utilized in a MOS device despite the need to cap the channel with a highly dislocated Si layer.
The effect of Mg in Ag(Mg)/SiO2/Si multilayers on adhesion, agglomeration, and resistivity after annealing in vacuum at 200 to 500 have been investigated. The annealing of Ag(Mg)/SiO2/Si multilayers produced surface and interfacial MgO layers, resulting in MgO/Ag(Mg)/MgO/SiO2/Si structure. The presence of surface MgO provided the passivation against air, thus leading to the significantly enhanced resistance to agglomeration. In addition, the resistivity of Ag(Mg) film decreased by lowering Mg content and increasing the annealing temperature as well. Furthermore, Ag adhesion to SiO2 was improved due to the formation of the interfacial MgO layer resulting from the reaction of segregated Mg with SiO2. Also, the negligible solubility of Si in Ag prevented the dissolution of free silicon produced from the reaction, Mg + SiO2 = MgO + Si, which was in contrast with the dissolution of a significant amount of silicon released from the SiO2 substrate in Cu(Mg)/SiO2/Si multilayers after annealing at high temperature, e.g., 400. The dissolved Si in Cu caused the rapid increase in resistivity in Cu(Mg)/SiO2/Si.