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C-V and G-V Measurements Showing Single Electron Trapping in Nanocrystalline Silicon Dot Embedded in MOS Memory Structure

Published online by Cambridge University Press:  15 March 2011

Shaoyun Huang
Affiliation:
Research Center for Quantum Effect Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro-ku, Tokyo 152-8552, JAPAN
Souri Banerjee
Affiliation:
Research Center for Quantum Effect Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro-ku, Tokyo 152-8552, JAPAN
Shunri Oda
Affiliation:
Research Center for Quantum Effect Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro-ku, Tokyo 152-8552, JAPAN
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Abstract

We prepared a SiO2/nanocrystalline Si (nc-Si)/SiO2 sandwich structure. A clear positive shift in C-V and G-V curves due to electrons trapped in nc-Si dots has been observed at room temperature. The peak in conductance around flat band condition indicates that a trap event had occurred where an electron is stored per nc-Si dot. A logarithmic charge loss function is found and this discharging process is independent of the thermal activation mechanism. The longer memory retention time and logarithmic charge loss in the dots are explained by a “built-in” electric field through the tunnel oxide, which varies with time, resulting in a variable tunneling probability. The electric repulsion induced by the built-in electric field hinders the discharging of electrons remained in the dots.

Type
Research Article
Copyright
Copyright © Materials Research Society 2002

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References

1. Tiwari, S., Rana, F., Hanafi, H., Hartstein, A., Crabbé, E., and Chan, K., Appl. Phys. Lett. 68, 1377 (1996).Google Scholar
2. Dutta, A., Hayafune, Y. and, Oda, S., Jpn. J. Appl. Phys. 39, 855 (2000).Google Scholar
3. Guo, L. J., Leobandung, E., and Chou, S. Y., Science 275 649 (1997).Google Scholar
4. Nakajima, A., Futatsugi, T., Kosemura, K., Fukano, T., and Yokoyama, N., Appl. Phys. Lett. 70, 1742 (1997).Google Scholar
5. Shi, Y., Saito, K., Ishikuro, H., and Hiramoto, T., J. Appl. Phys. 84, 2358 (1998).Google Scholar
6. Hinds, B. J., Yamanaka, T., and Oda, S., J. Appl. Phys. 90, 6402 (2001).Google Scholar
7. Kohno, A., Murakami, H., Ikeda, M., Miyazaki, S., and Hirose, M.: Ext. Abstr. 1998 Int. Conf. Solid State Devices & Materials, Hiroshima, 1998, p.174.Google Scholar
8. Kim, Y., Park, K. H., Chung, T. H., Bark, H. J., and Yi, J. Y., Appl. Phys. Lett. 78, 934 (2001).Google Scholar
9. Kapetanakis, E., Normand, P., and Tsoukalas, D., Appl. Phys. Lett. 77, 3450 (2000).Google Scholar
10. Ifuku, T., Otobe, M., Itoh, A. and, Oda, S., Jpn. J. Appl. Phys. 36, 4031 (1997).Google Scholar
11. Kerber, M., J. Appl. Phys. 74, 2125 (1993).Google Scholar
12. Busseret, C., Souifi, A., Baron, T. and, Guillot, G., Supperlattices and Microstructures, 28, 493 (2000).Google Scholar
13. Sze, S. M., Physics of Semiconductor Devices, (New York, Wiley, 1981) Chap. 7.Google Scholar
14. Fleischer, S., Lai, P. T., and Cheng, Y. C., J. Appl. Phys. 72, 5711 (1992).Google Scholar