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Capacitance-Voltage (C-V) Hysteresis in the Metal-Oxide-Semiconductor Capacitor with Si Nanocrystals Deposited by the Gas Evaporation Technique

  • Puspashree Mishra (a1), Shinji Nozaki (a1), Ryuta Sakura (a1), Hiroshi Morisaki (a1), Hiroshi Ono (a1) and Kazuo Uchida (a1)...

Abstract

Capacitance-Voltage (C-V) hysteresis was observed in the Metal-Oxide-Semiconductor (MOS) capacitor with silicon nanocrystals. The MOS capacitor was fabricated by thermal oxidation of Si nanocrystals, which were deposited on an ultra-thin thermal oxide grown previously on a p-type Si substrate. The Si nanocrystals were deposited by the gas evaporation technique with a supersonic jet nozzle. The size uniformity and the crystallinity of the Si nanocrystals are found to be better than those fabricated by the conventional gas evaporation technique. The C-V hysteresis in the MOS capacitor is attributed to electron charging and discharging of the nanocrystals by direct tunneling though the ultra-thin oxide between the nanocrystals and the substrate. The flat-band voltage shift observed during the C-V measurement depends on the size and density of the nanocrystals and also on the magnitude of the positive gate bias for charging. The retention characteristic is also discussed.

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Capacitance-Voltage (C-V) Hysteresis in the Metal-Oxide-Semiconductor Capacitor with Si Nanocrystals Deposited by the Gas Evaporation Technique

  • Puspashree Mishra (a1), Shinji Nozaki (a1), Ryuta Sakura (a1), Hiroshi Morisaki (a1), Hiroshi Ono (a1) and Kazuo Uchida (a1)...

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