The in-situ processing of silicon dielectrics by rapid thermal processing (RTP) is described. RTP includes here three basic sequentially performed processes: wafer cleaning, oxidation and annealing. The insitu cleaning allows for reduction of chemical and native oxides and silicon surface chemical polish, resulting in interface density of states as low as 5×l09 cm-2eV-1. Kinetics of oxide growth indicates an activation energy of 1.4 eV for the initial linear oxidation rate.

Thin gate oxides of 30 to 150 Å have been grown in a rapid thermal annealing machine. Experiments were performed in the temperature range of 1000 to 1250°C for an oxidation time of 5 to 60 s. The fairly extensive kinetics data show that linear growth occurs with an activation energy Ea of 1.4 eV for the 5-60 s period. The oxide homogeneity was evaluated and gave a value of 1.9 A for a mean oxide thickness of 102 A. The electrical characteristics of Al-gate capacitors were assessed by C-V and I-V measurements. Rapid thermal nitridation of a 96 A SiO2 has been performed at a temperature of 1150°C for a nitridaticn time up to 150 s. An average breakdown field of 14.6 MV/cm has been obtained for MIS capacitors. High resolution TEM show a good interface SioXNY-Si.

A self-aligned titanium silicide process which combines the use of ion-beam mixing and rapid thermal processing (RTP) has been developed for CMOS VLSI applications. Shallow silicided junctions are formed by implanting dopants into silicide layers previously formed by ion-beam mixing with Si ions and low temperature annealing, and the subsequent drive-in of the implanted ions into the Si substrate during high temperature RTP. In addition, the formation of TiN on TiSi2 is achieved simultaneously during this process as a diffusion barrier for Al metallization. Short-channel MOS transistors with SALICIDE structure have been successfully fabricated and tested. Results of the impurity diffusion in silicide layer, the impurity segregation at both silicide/Si and oxide/silicide interfaces, contact stabilit of Al/TiN/TiSi2 structure, and device characteristics will be reported. Issues related to this process and its application to submicron device fabrication are discussed and foreseeable problem areas identified.

An extremely reliable TiSix/TiNx diffusion barrier was formed by the rapid thermal annealing of a thin Ti layer which was sputtered into the contacts before Al metallization. The effects of this barrier metal process on the material properties of heavily implanted n+ and p+ regions were studied. The TiNx-to-TiSix thickness ratio is determined by the dominant reaction at the sintering temperature. Arsenic implanted in the substrate tends to substantially retard the silicidation of Ti. Substantial redistribution of both B and As across the silicide layer was observed during rapid thermal annealing. Film stress was found to be greatly affected by the annealing temperature. Contact resistance, contact electromigration and thermal stability of the structure were also investigated.

TiN and TiN/TiSi2 films, formed by reacting titanium sputtered onto source-drain and field areas, may be used as local interconnects, low resistance plated junctions, and diffusion barriers. This paper discusses the application of RTP to the low temperature reaction of titanium on silicon and oxide substrates. By adjusting temperature and ambient the nitridation and silicidation reactions may be controlled to provide the desired TiN-TiSix thickness ratio. The advantages of ammonia ambient are discussed.

TiSi2 films produced from co-sputtered Ti/Si mixtures by rapid thermal processing at temperatures around 630°C were found to have a higher resistivity than films formed by the solid state reaction of deposited Ti with (100) silicon during asimilar anneal. Diffraction studies indicated the films comprised of the C49 phase only. It is argued that the resistivity difference arises from the extremely high (3106cm−1) stacking fault density in the annealed co-sputtered layers.

Sputtered titanium films with thicknesses in the range of 300 to 1200Å were processed in a commercial rapid annealing system to form TiSi2 films. The films were first reacted at low temperatures (500-700°C), etched in ammonia/peroxide solution, and then reacted at 850-900°C to simulate a typical self-alignedsilicide (salicide) process. A method to correctfor dynamic temperature nonuniformities and the resulting etch nonuniformities will be discussed. Sheet resistance maps of the resulting films will be presented. In addition, film properties were measured as a function of annealing ambient in particular, the effects of oxygen contamination were studied.

We have investigated the formation of titanium silicide films sputter deposited from a high purity (99.995%) composite TiSi2.2 target. The films, sputtered at a rate of 3.7 nm/sec, were deposited on Si(100), Si02 , and N+ Poly-Si substrates at temperatures ranging from room temperature to 425°C. Room temperature depositions produced amorphous films, while heated substrate depositions formed crystalline films with a metastable C49 TiSi2 structure. Rapid thermal processing of these films at temperatures higher than 700°C resulted in the formation of a stable C54 TiSi2 structure. Stoichiometry of the deposited films over a 10 cm diameter wafer was found to be independent of the substrate temperature. Stress in the films was measured as a function of deposition and annealing parameters. The amorphous films showed a tensile stress of about 0.1 GPa, while films deposited on substrates at 425°C had an order of magnitude higher tensile stress level.The resistivity measured on the 400°C deposited films was about half of that obtained with the films deposited at roomtemperature. A comparison between films deposited on a hot substrate and those which were rapid thermal processed is presented.

Interest in CoSi2 as a metallization for very large scale integrated circuits (VLSI) has grown rapidly since the recent demonstration of a simple self-aligned process performed by rapid thermal annealing.1-4 Using a rapid thermal anneal (RTA) to directly silicide Co on Si yields smooth low-sheet-resistance films with little or no lateral diffusion and low contact resistance. In addition, it has been shown that rapid thermal annealing can result in reasonable quality epitaxial CoSi2 on (111) Si wafers.5 An important advantage of CoSi2 over the more commonly used TiSi2 metallization is the relative simplicity of its self-aligned silicidation process. Due to the low reactivity of Co with SiO2, a simple two-step self-alignment process is possible instead of the three-step process necessary with TiSi2.6 The primary disadvantage of CoSi2 is the amount of Si consumed for equal silicide sheet resistance. For example, to yield a silicide sheet resistance of 1.5 1/LD, Van den Hove 4 finds that compared to the TiSi, process, the CoSi, process would consume an additional 24 nm of Si. (This disadvantage can be minimized if very shallow junctions can be formed under the CoSi2.)

Silicide formation induced by rapid thermal annealing (RTA) and conventional furnace annealing (CFA) in bilayers of sequentially deposited films of amorphous silicon and polycrystalline Co or Ni is studied with RBS, X-ray diffraction and TEM. Particular attention is paid to the reliability of the RTA temperature measurements in the study of the growth kinetics of the first interfacial compound, Co2Si and Ni2Si, for both RTA and CFA. It is found that the same diffusion-controlled kinetics applies for the silicide formation by RTA in argon and CFA in vacuum with a common activation energy of 2.1+0.2eV for Co2Si and 1.3+0.2eV for Ni Si. Co and Ni atoms are the dominant diffusing species; during silicide formation by both RTA and CFA. The microstructures of the Ni-silicide formed by the two annealing techniques, however, differs considerably from each other, as revealed by cross-sectional TEM studies.

Raman Scattering as a technique for studying the formation of tungsten silicide is presented. The tungsten silicide films were formed by rapid thermally annealing tungsten films that were sputter deposited on silicon substrates. The Raman scattering data is correlated with data from resistivity measurements, Auger and Rutherford Backscattering measurements, and scanning electron microscopy.

RTA has been investigated for a variety of applications including implant anneal and modification of poly silicon. However, little has been reported on the integration of RTA into actual process flows. We describe here results for bipolar IC's with RTA for the fabrication of shallower junctions and lower sheet resistance (Rs) poly electrodes. For a successful bipolar IC, not only are good diode characteristics and related transistor parameters important, but also, resistor behavior, uniformity, and yield are critical. An AG Heatpulse system was used to successfully anneal the emitter implant of 2.0 um design rule bipolar IC's. The yield and variation in gate delay were comparable to furnace annealed counterparts. These results are especially encouraging since both transistor performance and resistor matching are critical for the circuits tested. However, significant improvement in gate delay was not observed.

The activation of ion implanted emitters for two types of NPN bipolar junction transistors ( BJT ) by rapid thermal processing (RTP) was evaluated. The dopant profiles and the resultant junction depths were measured for various thermal cycles, using spreading resistance profile technique. The electrical characteristics of the transistors were then determined and compared to the standard furnace processes. The common emitter current gain values, hFE, for arsenic emitters were low and phosphorous emitters exhibited improved or comparable betas. The breakdown voltages in common emitter configuration, BV,CEO, BVcEs and BVEBO were comparable or better than the furnace annealed samples and no evidence of transistor leakage was observed.

Rapid thermal processing has previously been observed to affect the dielectric integrity of thin oxides.' In order to study this phenomenon in more detail, we have fabricated a set of wafers with 290 Å thick gate oxide and patterned pads of 2000 Å thick doped polysilicon. Some of the pads were patterned with a wet etch, while others were dry etched in a commercial reactive ion etcher (RIE), which is suspected to be a damaging process. To simulate a self-aligned MOS process, some of the patterned wafers were also ion implanted with 70 keV, 2E15 As+/cm2 . Subsequently, all of the wafers were rapidly annealed in a Varian RTP-800 lamp annealer under a variety of conditions (lO00-1100°C, 10-30 sec), and the breakdown characteristics of the MOS capacitors were measured. A few control samples were annealed in a furnace. It was found that the rapid annealing cycle without ion implantation or dry etching caused no deterioration of the oxide quality. However, rapid annealing after either RIE or implantation does result in oxide breakdowns at lower voltages, with those capacitors having higher perimeter-toarea ratios affected to a greater degree. The effect of capacitor shape and annealing conditions on breakdown statistics and uniformity will be presented and discussed in light of possible ion bombardment damage during RIE and oxide charging during ion implantation. Several mechanisms explaining the breakdown properties will be discussed.

The advantages of Silicon-on-Insulator (SO) devices over bulk Silicon devices are well known (speed, radiation hardened, packing density, latch up free CMOS,). In recent years, much effort has been made to form a thin, buried insulating layer just below the active device region. Several approaches are being developed to fabricate such a buried insulating layer. One viable approach is by high dose, high energy oxygen implantation directly into the silicon wafer surface (1-3). With proper implant and annealing conditions, a thin stoichiometric buried oxide with a good crystalline quality silicon overlayer can be formed on which an epitaxial layer can be grown and functional devices and circuits built. As SO1 circuits become market viable, mass production tools and techniques are being developed and evaluated. Of particular interest here is the evaluation of high current oxygen implantation with rapid thermal processing on the electrical characteristics of the oxide-silicon interfaces, the silicon overlayer and the thermally grown oxide on the top surface using measurements on gated diodes and guarded capacitors.

The technique of rapid thermal processing (RTP) has evolved from research laboratory efforts to quickly heat small pieces of semiconductor material using pulsed or scanned lasers to high throughput, production RTP equipment capable of rapidly heating eight-inch silicon wafers to greater than 1000 deg C in 10 seconds. Furthermore, the initial application of annealing ion implantation damage has expanded to include silicide formation, oxide reflow, contact formation, hillock control and more recently oxidation and nitridation. Nearly a dozen vendors now produce RTP equipment and the potential user must answer the question — “Which equipment is best for me?” The researcher's principal concerns for RTP equipment are flexibility and control while the production engineer wants unifomity, reproducibility, and a reasonable throughput. Meanwhile, the device designer wants a “safe” process with no contamination or other adverse device degradation effects. This paper will focus on these and other issues associated with the use of rapid thermal processing from a user' perspective including some thoughts on where RTP may be headed in the future.

Temperature-time profiles obtained by an optical pyrometer and a mechanically contacted thermocouple are first presented it appears that the thermocouple response is sensitive to the pressure in the processing chamber. The authors suggest that, in vacuum, the thermocouple is thermally isolated from the wafer, until the temperature is high enough for thermal radiation exchanges to occur. Experimental evidence of the influence of thermal history, and of gas pressure and flow, on temperature drop at periphery of the wafer is then given.

Slip is a primary concern in Rapid Thermal Processing (RTP). Diagnostics for slip are compared, including: visual inspection, differential interference contrast microscopy (Nomarski), X-ray topography, decorative etching and optical surface scanning. Data from each technique are presented. RTP control parameters (temperature uniformity, heat up and cool down rates, edge cooling) and substrate parameters (wafer size, oxygen content, edge damage) which may have an effect on slip are discussed. Typical results for implant annealing sequences on a water-wall DC arc lamp RTP system are presented and used to suggest techniques for process optimization.

A new Rapid Thermal Processing technique based on heating by irradiation from CO2 laser is presented. It is particularly suitable for thermal treatment of low melting temperature materials such as annealing implantation induced damage in compound semiconductors.

Short time heating of the sample is achieved by its contact with a quartz plate heated by photons from a CW CO2 laser. The quartz serves both as an absorbing medium for the radiation and as a proximity cap. Steady state temperature can be obtained by the simultaneous heating of the sample by the laser and its cooling by a jet of N2 gas.

The present technique, when applied to ion implanted InSb (TA<450°C, t=10 seconds), leads to removal of the implantation damage which is comparable to that obtained by furnace or flash lamp (Heatpulse™)annealing.

Limited Reaction Processing (LRP) is a new technique which combines Rapid Thermal Processing (RTP) and Chemical Vapor Deposition (CVD). The added temperature control provided in rapid thermal processing enables the use of substrate temperature as a reaction switch. In addition, rapid thermal technology has been shown to provide other advantages for chemical vapor deposition of Si and III–V materials. Results are presented for group IV materials including epitaxial Si, SiGe alloys, SiO2 , and polysilicon. MOSFETs have been demonstrated and sensitive tests of interface quality are presented, paving the way for future bipolar transistor fabrication. III–V materials such as GaAs, AlGaAs, InGaAs have been grown. GaAs electron mobilities are the best reported for material grown using trimethylarsenic. As-ambient rapid thermal anneals of GaAs have also been performed.