Problems in semiconductors and integrated circuits range from crystalline defects to contamination to misformed structures. They may be due to a single event (e.g. foreign particle) or a complex interaction between materials, processes, and environment. Many clues for the cause of these problems can be obtained from in-line measurements, such as electrical device behavior or layer thickness, but it is often not until after a defect or abnormal structure is seen that it is fully understood. The method of “seeing” must allow the normal to be distinguished from the abnormal and ultimately the reason for the difference to be determined. Vast amounts of data are often generated to electrically understand a defect or determine the reliability implications of a problem but it is often not until microscopic analysis is performed that the problem is fully revealed. It is not uncommon for just a small number of images bring to light the origin of a problem and lead to a solution.

The sub-micron era in 1C process technology has been characterized by ever shrinking device geometries. When the minimum feature size of 0.5 micron was reached, a significant inflection in the usefulness of optical microscopy occurred. Seemingly routine Fab activities such as the use of the optical microscopes to determine the quality of the metal etch were no longer possible. At the same time, an increased use of defect inspection tools such as KLA and Tencor was required to insure stable process quality. These and other factors combined to hasten the introduction of multiple defect review scanning electron microscopes into the modern 1C Fab. This trend has accelerated during the process development of 0.25 micron technology. Accordingly, as leading 1C manufactures introduce production 0.25 devices, it is not unusual to find as many as six such instruments installed in a modern development or fabrication facility. As such, these instruments, commonly called Defect Review Tools (DRT's) constitute an increasing share of the Fab equipment set.

The complexity of today’s commercial semiconductors has contributed to tremendous gains in device performance; millions of transistors are now packed into each square centimeter of silicon. The reduction of scale occurring within the semiconductor industry places extraordinary new demands on transmission electron microscopy: TEM is becoming a required precision measurement tool for manufacturing and a necessary analytical tool for R&D and failure analysis support. This paper reviews the industry’s needs for advanced TEM sample preparation, imaging and microanalysis and outlines the challenges presented to the TEM community as device dimensions continue along the National Technology Roadmap.

In the semiconductor industry, TEM is applied to process debugging, yield engineering, tool qualifications, single-bit failure analyses, and new process development. A large fraction of the analysis effort focuses on transistor, metal, interconnect and dielectric structures grown on and into the Si wafer. Fig. 1 shows a TEM image of a multilayer metal in a near-current generation microprocessor to illustrate the scale and nature of complexity.

The scalability requirements of higher and higher density DRAM and logic CMOS devices has popularized the salicide process for source to drain connections using TiSi2 and ( more recently ) CoSi2.

The desirability of these salicide processes is well documented with low sheet resistivity properties offering improved access time in DRAM and faster microprocessor speeds.

Besides the obvious drawback in temperature stability of these salicides, the irregular reaction of titanium or cobalt with silicon during RTA processing can result in irregular or “rough” surface features in the salicide. Submicron contaminants (especially metallic species) introduced during in-line electrical test of Kerf structures with high wettability are not easily dislodged by conventional aqueous/ultrasonic cleaning steps. Solvent process cleaning steps can leave residues in the irregular “rough” salicide surface leading to interfacial films between the salicide and the subsequent via connection to overlying bit lines ( or metal one lines ).

Titanium suicides have low resistivity, low contact resistance, and are widely used as interconnects in electronic devices. The most desirable structure is the C54 variant of titanium disilicide (TiSi2). It is typically formed during thermal annealing by a polymorphic transformation from the C49 TiSi2 structure. The C49 to C54 transformation has been studied extensively and there has been substantial effort to devise ways in which to lower the temperature associated with this transformation. This research uses high-resolution imaging (HREM), convergent-beam diffraction (CBED), and energy-dispersive X-ray microanalysis (EDS) to study the development of suicide morphology in response to rapid thermal annealing (RTA). Two sets of specimens have been studied: (i) 32nm Ti thin films on undoped single-crystal Si substrates [Ti/Si] and (ii) 32nm Ti films separated from an undoped single-crystal Si substrate by a 0.12nm thick Mo interlayer [Ti/Mo/Si]. This paper shows structures formed after RTA at a ramp rate 3 °C/sec to 750 °C with a hold of 1 sec

Future Si microelectronic devices will require increasingly stringent limits on transition-metal impurities. There is thus a need to develop new methods for impurity gettering that rely on gettering sites that are active for arbitrarily small impurity concentrations, below the characteristic solid solubility at which metal suicides precipitate. These sites must also be highly preferred relative to solution sites in the Si matrix even at elevated temperatures. One such method has been developed that is also expected to be compatible with front (device) side gettering enabling smaller diffusion lengths for lower processing temperatures. This method involves boron implantion in the front side to levels above the boron-saturation limit and annealing to generate the gettering sites. The gettering layer is introduced at a depth beneath the device zone through appropriate choice of implantation energy. SIMS compositional profiling shows transition metals are strongly gettered within the boron-supersaturated layer. The purpose of this study was to identify the structure and composition of the gettering sites within the boron-supersaturated layer.

Group IV based alloys have received considerable attention in recent years, because of the possibility to tailor the band gap of the material system with respect to that of Si. Significant results have already been achieved with Si-Ge system, where the band gap of pseudomorphic Si1-xGex alloys is smaller than that of Si. Introduction of C onto substitutional lattice sites in Si has been proposed as a possible alternate method for tailoring the electronic properties of Si. Carbon incorporation into Si substitutionally could result in alloys whose band gap would be a function of carbon concentration and lie between the values for silicon (E =1.1 eV) and β-SiC (Eg = 2.3 eV). However, due to the low-equilibrium solubility limit of C in Si, 3.5x1017cm−3 at the eutectic temperature, highly supersaturated and metastable layers are essential to significantly alter strain and electrical properties of the alloys.

In our present study, we have synthesized and characterized Si1-yCy (0.04 < y < 0.20) films grown on (001) Si substrates by ultra-high vacuum chemical vapor deposition at 625°C.

Investigations of the atomic structure of Si-SiO2 interfaces have mostly been performed with high resolution transmission electron microscopy. However, the interpretation of the phase contrast in the amorphous phase at the interface is not unique. While Ourmazd et al. concluded on a crystalline phase at the Si-SiO2 interface, Akatsu and Ohdomari attributed the same contrast to an interface roughness parallel to the incident electrons.

We investigated the Si-SiO2 interface by studying the ELNES of the O-K edge with the spatial difference technique with a dedicated STEM with l00kV (VG HB501 UX). Also the interface was studied by Z-contrast imaging with a 300 kV dedicated STEM (VG HB603 U). Silicon wafers (110) were first thermally oxidised to produce a SiO2 layer. The thermally grown oxide was used as a substrate for liquid phase epitaxy of silicon, given two {111} Si-SiO2 interfaces in the sample grown by two different techniques (see fig. 1).

The growth of thin films on dissimilar substrates is of great technological importance for modern optoelectronic devices. However, device applications are currently limited by lattice mismatches between the film and substrate that invariably lead to defects detrimental to device performance. It is therefore of key importance that the mechanisms leading to the formation of these defects are understood on the fundamental atomic level. Correlated atomic resolution Z-contrast imaging and EELS in the STEM is a unique methodology by which this information can be obtained. In this paper, the application of this methodology to determine a novel graphoepitaxial growth mechanism for CdTe on (001)Si is demonstrated, and its potential for the study of GaN is discussed.

Fig.la shows a high resolution Z-contrast image of a cross sectional view of the CdTe/Si interface showing clearly the CdTe and Si dumbbells. Due to the differences in atomic number, the location of the interface is clear.

Microelectronic processes now involve multilayer structures of different materials. It is important to control accurately the thickness and composition of these materials during their processing. The determination of these two physical parameters are usually performed by Elastic Recoil Detection (ERD), by Auger Electron Spectroscopy (AES) and Transmission Electron Microscopy (TEM). However, these techniques are not suitable for analysis on a routine basis. In this context, a quantitative procedure based on EDS X-ray microanalysis in the Scanning Electron Microscope has been developped because of its availability and its speed of analysis. However, this technique requires several measurement of K ratio taken at different voltages which is time consuming. With the advent of Field Emission Gun Scanning Electron Microscopes (FEGSEM), X-ray line scans taken at low electron beam voltage with an EDS system may be an alternative. In this paper, preliminary results using this technique on multilayered materials are presented.

To investigate this characterization technique, a AlSiCu(200 nm)/TiN(95 nm)/Ti(40 nm) multilayer metallization structure deposited on Si substrate was used. EDS X-ray line scans were obtained with a Hitachi S-4500 FEGSEM coupled with a Link ISIS 300 EDS system.

As the size of integrated circuit devices continues to decrease, the ratio of interfacial area to volume increases and the dimension of thin films shrinks to the order of tens of nanometers. In such circumstances, the interfacial reactions, which are frequently accompanied with nanometer scale local failures, become a dominant mechanism for the breakdowns of the devices at high temperatures. This makes transmission electron microscopy (TEM) take a unique role in the research of Si metallization. In situ techniques have succeeded to reproduce and observe such real time reactions in the TEM. Moreover, after the introduction of the field emission gun systems(FEG), there have been enormous improvements in the spatial resolution and performance of x-ray energy dispersive spectroscopy (EDS) and electron microdiffraction. In the present work, two case studies of local failure were successfully investigated by combining these techniques: TiN diffusion barrier breakdown between Si and Al, and TiN electrodes on tantalum pentoxide (Ta2O5) capacitors for 1 Gigabit DRAM.

Ion implantation of arsenic and phosphorus is a common practice in silicon devices for the formation of transistor source/drain regions. We used a TEM equipped with EDX capabilities to investigate effects of ion implantation in actual devices before and after annealing. A 200 kev field emission gun TEM was used in this study. Two implant cases were studied here. Both samples are p-type, (100) Si wafers.

Figure 1 shows the microstructure in a common source region of a silicon device after being implanted by phosphorus (4x1014 cm−2 at 30 kv, 0°), while Figure 2 shows a similar region for arsenic implantation (5x1015 cm−2 at 45 kv, 0°). No screen layer was used during implantation. The phosphorus implant results in a ˜0.05 μm amorphous layer sandwiched between heavily damaged crystalline silicon. High resolution images reveal a rough amorphous/damaged crystalline boundary and high density defects due to silicon lattice displacements.

Titanium nitride (TiN) films are used as anti-reflection coatings (ARC) on aluminum (Al) films to facilitate lithography processes during multilevel metallization for the manufacture of integrated circuits on silicon-based (Si) semiconductor devices. It is generally accepted in the literature that the microstructure of multilevel metal stacks is influenced by the texture of the substrate. For the case of interconnect materials used in the semiconductor industry, a typical metal stack is as follows: Titanium/Titanium Nitride/Al-alloy/ARC-Titanium Nitride. The Ti/TiN layer underneath the Al-alloy film is used as a barrier stack to prevent junction spiking. The Ti/TiN underlayer also determines the growth conditions (crystallography and orientation relationships) of the subsequent Al-alloy film.

This study focuses on the microstructural characterization of the ARC-TiN layer on Si-oxide and Ti/TiN/Al-alloy substrates that are fabricated under similar conditions using conventional physical vapor deposition (PVD - sputtering) techniques. The ARC-TiN microstructure was investigated by transmission electron microscopy (TEM) using a Philips EM430 operating at 300 kV.

Analytical transmission electron microscopy (AEM) equipped with a field emission gun has made it possible to analyze chemical information at local spots or interfaces with a very small electron probe. This technique has been applied to assist in process development and addressing certain reliability issues in silicon devices.

Figure 1 shows an example of applications of AEM to a 0.5 μm transistor. An oxide bump is found to be located in the middle of a transistor. A very thin layer (20 Å) is on the top of the oxide bump. Using EDS, the bump is determined to be a silicon oxide, but EDS failed to analyze the thin layer. Electron energy loss spectroscopy detects nitrogen in this residual layer (Fig. la), suggesting that the residue is a thin nitride. This residual nitride is caused by the incomplete removal of the nitride mask after field oxidation. This nitride residue blocks the subsequent removal of the buffer oxide between the nitride mask and the substrate.

Silicon-on-Insulator is the leading technology for VLSI fast speed processors and low voltage applications. SIMOX (Separation by Implantation of Oxygen) is a subset of SOI with a high quality top silicon layer onto which VLSI circuitry is placed. SIMOX processing begins with a high energy, high current implantation of a large dose of O+ ions to penetrate the wafer’s surface to form the buried oxide and top silicon layers. This implantation creates numerous precipitates and a large damage region. Therefore a multi-step anneal is used to improve the quality of the top silicon layer by significantly reducing precipitate and dislocation densities, to create smooth interfaces, and to remove any ion residual damage. Using TEM, this study traces the defect formations through the various processing steps, with the objective to arrive at device quality.

The SIMOX wafers were implanted with an oxygen ion implant dose of 5xl017cm−2, and then subjected to multiple implantation and anneal steps, bringing the final oxygen ion dose to 1.5xl018cm−2[1].

Group III-nitride thin films are currently of great interest for use in wide-bandgap semiconductor applications including UV lasers and light emitting diodes (LEDs). Sapphire (a-Al2O3) is currently the substrate of choice for the growth of GaN despite a large lattice mismatch. Growth of high quality GaN epilayers typically involves the deposition of a buffer layer of either AIN or GaN at a temperature well below that used for the growth of the active GaN layer. It has been found empirically that nitridation of the sapphire surface with nascent nitrogen prior to growth of the buffer layer results in a substantial improvement in film quality. Using a novel ultra-high vacuum (UHV) in-situ TEM with in-situ RMBE, we have studied the nitridation of the (0001) sapphire surface using transmission and reflection electron microscopy (REM), reflection high energy electron diffraction (RHEED) and Auger electron spectroscopy (AES).

An electron-transparent sapphire TEM sample was annealed at 1400°C for 12 hours in flowing oxygen, to form atomically flat surfaces for our investigation.

A recent process technology to manufacture bipolar junction transistors utilizes polysilicon emitters. Polysilicon is deposited, appropriately doped to form both NPN and PNP transistors, and exposed to temperatures that result in grain growth. Since polysilicon is in contact with Si( 100) at the emitter, base, and collector (Fig. 1), solid phase epitaxial regrowth might also occur. Production runs with this structure occasionally produce transistors with low current gain. High and low gain NPN and PNP transistors were characterized by transmission electron microscopy.

Vertical sections through NPN/PNP transistor arrays were made by the wedge technique, low-angle ion milled to electron-transparency, and viewed at 200 KV. The grain size of the polysilicon on oxide was recorded and estimated. The extent of epitaxial regrowth was quantified for each of the Si (100) contact areas. Convergent Beam Electron Diffraction (CBED) was used to confirm the orientation of the presumed regrown polysilicon.

The performance of electronic devices, such as dynamic random access memories, is degraded by contamination due to impurity atoms as well as crystalline imperfections created during processing. The evaluation of those degradation causes is generally done using an analytical transmission electron microscope. The information obtained, however, is limited to two-dimensional images of the specimen as seen from a single direction. Advanced semiconductor devices with finer-pattern structures are expected to exhibit larger fluctuations in device performance due to the spatial distribution of the faults. A new method has thus been examined to determine the atomic species and to reconstruct three-dimensional (3-D) images of the specimen structure by using high-angle hollow-cone dark-field transmission electron microscopy (HADF-TEM).

A incident angle controller was added to a conventional TEM to control the electron-beam deflection coils. This enables the incident electron beam to be inclined and rotated, providing hollow-cone illumination of the specimen, as shown in Fig. 1.

In the mid to late 80's there was considerable effort directed at the hetroepitaxial growth of III-V's (GaAs, GaP and InP) on Si substrates for solar cell applications. The primary incentive for this work was the cost reduction of expensive substrate materials. This is particularly important when considering large scale production of terrestrial photovoltaic modules. In the U.S. these efforts produced cell efficiencies up to 21% and continued development of this solar cell structure is currently being pursued in Japan. Similar cost effective structures are being investigated at NREL such as the growth of polycrystalline GaAs films on inexpensive glass substrates for solar cell applications. Polycrystalline films, however, tend to contain a high density of grain boundaries which are regions for carrier recombination and enhanced dopant diffusion which can limit cell performance. In order to reduce the detrimental effects of grain boundaries, the growth of large grain (hence low boundary area) GaAs is being investigated

Cubic boron nitride films were prepared by helicon wave plasma CVD process on (100) Si. The film deposited under the intense impact of energetic ions is usually delaminated from the substrate after deposition. The delamination behavior of c-BN film was investigated with transmission electron microscopy. It is found that moisture in the air, surface roughness of the film and substrate, as well as severe compressive stresses in the film are the primary contributors to film delamination. An aqueous oxidation was verified by EDXS analysis, which generate local stress by volume expansion at the crack region in the c-BN layer.

The cross-sectional TEM micrograph of c-BN film in Fig. 1 shows that a very thin layer of h-BN is deposited before the c-BN layer starts to grow at an early stage of film growth. A columnar structured thin h-BN layer about 20 nm thickness at the interface is clearly separated from the c-BN layer in an aspect of microstructure.