A recent process technology to manufacture bipolar junction transistors utilizes polysilicon emitters. Polysilicon is deposited, appropriately doped to form both NPN and PNP transistors, and exposed to temperatures that result in grain growth. Since polysilicon is in contact with Si( 100) at the emitter, base, and collector (Fig. 1), solid phase epitaxial regrowth might also occur. Production runs with this structure occasionally produce transistors with low current gain. High and low gain NPN and PNP transistors were characterized by transmission electron microscopy.

Vertical sections through NPN/PNP transistor arrays were made by the wedge technique, low-angle ion milled to electron-transparency, and viewed at 200 KV. The grain size of the polysilicon on oxide was recorded and estimated. The extent of epitaxial regrowth was quantified for each of the Si (100) contact areas. Convergent Beam Electron Diffraction (CBED) was used to confirm the orientation of the presumed regrown polysilicon.