Ion implantation of arsenic and phosphorus is a common practice in silicon devices for the formation of transistor source/drain regions. We used a TEM equipped with EDX capabilities to investigate effects of ion implantation in actual devices before and after annealing. A 200 kev field emission gun TEM was used in this study. Two implant cases were studied here. Both samples are p-type, (100) Si wafers.

Figure 1 shows the microstructure in a common source region of a silicon device after being implanted by phosphorus (4x1014 cm−2 at 30 kv, 0°), while Figure 2 shows a similar region for arsenic implantation (5x1015 cm−2 at 45 kv, 0°). No screen layer was used during implantation. The phosphorus implant results in a ˜0.05 μm amorphous layer sandwiched between heavily damaged crystalline silicon. High resolution images reveal a rough amorphous/damaged crystalline boundary and high density defects due to silicon lattice displacements.