This contribution deals with the state of the art of studies concerning the fabrication of electric double-layer capacitors (EDLCs) also called super- or ultracapacitors and obtained using carbon nanotubes (CNTs) without exploiting Faradic reactions. From the first work published in 1997, EDLCs fabricated using carbon nanotubes as constitutive material for electrodes showed very interesting characteristics. It appeared that they could potentially outperform traditional technologies based on activated carbon. Different methods to fabricate the CNT-based electrodes have been proposed in order to improve the performances (mainly energy densities and power densities), for example filtration, direct growth on metal collector or deposition using an air-brush technique. In this contribution we will introduce the main works in the field. Finally, we will point out an emerging interest for supercapacitors fabricated on flexible substrates, exploiting the outstanding mechanical performances of CNTs, for new kinds of applications such as portable electronics.

A comparative study of the low temperature conductivity of an ensemble of multiwall carbon nanotubes and semiconductor nanowires is presented. The quasi one-dimensional samples are made in nanoporous templates by electrodeposition and CVD growth. Three different structures are studied in parallel: multiwall carbon nanotubes, tellurium nanowires, and silicon nanowires. It is shown that the Coulomb blockade regime dominates the electronic transport below 50 K, together with weak and strong localization effects. In the Coulomb blockade regime, a scaling law of the conductance measured as a function of the temperature and the voltage is systematically observed. This allows a single scaling parameter α to be defined. This parameter accounts for the specific realization of the “disorder”, and plays the role of a fingerprint for each sample. Correlations between α and the conductance measured as a function of temperature and voltage, as a function of the perpendicular magnetic field, and as a function of the temperature and voltage in the localized regime below 1 K have been performed. Three universal laws are reported. They relate the coefficient α (1) to the normalized Coulomb blockade conductance $G_{T}(\alpha)$, (2) to the phase coherence length $l_{\phi}(\alpha)$, and (3) to the activation energy $E_{a} (\alpha)$. These observations suggest a description of the wires and tubes in terms of a chain of quantum dots; the wires and tubes break into a series of islands. The quantum dots are defined by conducting islands with a typical length on the order of the phase coherence length separated by poorly conducting regions (low density of carriers or potential barriers due to defects). A corresponding model is developed in order to put the three universal laws in a common frame.


In order to utilise the full potential of carbon nanotubes/nanofibers, it is necessary to be able to synthesize well aligned nanotubes/nanofibres at desired locations on a substrate. This paper examines the preferential growth of aligned carbon nanofibres by PECVD using lithographically patterned catalysts. In the PECVD deposition process, amorphous carbon is deposited together with the nanotubes due to the plasma decomposition of the carbon feed gas, in this case, acetylene. The challenge is to uniformly nucleate nanotubes and reduce the unwanted amorphous carbon on both the patterned and unpatterned areas. An etching gas (ammonia) is thus also incorporated into the PECVD process and by appropriately balancing the acetylene to ammonia ratio, conditions are obtained where no unwanted amorphous carbon is deposited. In this paper, we demonstrate high yield, uniform, ‘clean’ and preferential growth of vertically aligned nanotubes using PECVD.

Plasma Enhanced Chemical Vapour Deposition is an extremely versatile technique for directly growing multiwalled carbon nanotubes onto various substrates. We will demonstrate the deposition of vertically aligned nanotube arrays, sparsely or densely populated nanotube forests, and precisely patterned arrays of nanotubes. The high-aspect ratio nanotubes (~50 nm in diameter and 5 microns long) produced are metallic in nature and direct contact electrical measurements reveal that each nanotube has a current carrying capacity of 107-108 A/cm2, making them excellent candidates as field emission sources. We examined the field emission characteristics of dense nanotube forests as well as sparse nanotube forests and found that the sparse forests had significantly lower turn-on fields and higher emission currents. This is due to a reduction in the field enhancement of the nanotubes due to electric field shielding from adjacent nanotubes in the dense nanotube arrays. We thus fabricated a uniform array of single nanotubes to attempt to overcome these issues and will present the field emission characteristics of this.

The selective growth of GaAs by HVPE was studied on (001), (110), (111)Ga and (111)As, GaAs patterned substrates by varying the I1I/V ratio. A kinetic modelling of the growth was developed, based upon the SEM observations of the growth morphologies as well as on experimental curve synthesis. The growth rate is written as a function of the diffusion fluxes of the adsorbed AsGa and AsGaCI molecules and takes into account the chlorine desorption by H2. 1.5 μm thick GaAs films were then fabricated on Si (001) by a confined epitaxial lateral overgrowth technique. These conformal films exhibit intense and uniform luminescence signals, showing that the dislocation densities of GaAs are lower than 105 cm−2. SEM analyses reveal that conformal growth fronts consist in (110) and (111)As A planes under the III/V ratios (superior to 1) which were tested.

Conformal epitaxy is an epitaxial growth technique capable of yielding low dislocation density III-V films on Silicon. In this technique, the growth of the III-V material occurs parallel to the silicon substrate, from the edge of a previously deposited III-V seed, the vertical growth being stopped by an overhanging capping layer. As an example, conformal GaAs layers on Silicon, presenting dislocation densities below 105cm−2, have been obtained using selective vapor phase epitaxy. These layers have then been used as high quality GaAs on Si substrates for subsequent vertical MBE regrowth of active structures. In this paper, we report on the integration of surface-emitting microcavity LEDs with their silicon drivers using this conformal growth technique. The global technology concept and the design of the active structures are first presented. The compatibility of the conformal growth technique with CMOS technology is then checked: the impact of the integration process on the performances of the drivers is for example quantified. Characterisations of the high crystalline quality of the conformal layers and of the LEDs structures grown on it are then shown. The electro-optical characteristics of the LEDs on Si are finally compared to those of reference LEDs on GaAs substrates in order to prove the efficiency of the integration procedure.

In this paper, we essentially discuss the material aspects of low temperature (≤ 600 °C) polysilicon technologies. Emphasis is put on the properties of polysilicon films, depending on the way they are obtained. Solid phase crystallisation as well as pulsed laser crystallisation processes are presented in some detail, together with thin film transistor characteristics. Although not yet stabilised and despite uniformity and reproducibility problems, laser crystallisation will probably end up being the technology of choice for the manufacture of large area electronics products, because it allows the fabrication of devices exhibiting superior properties, with a reduced thermal budget.

High purity amorphous silicon layers were obtained by ultrahigh vacuum (millitorr range) chemical vapor deposition (UHVCVD) from disilane gas. The crystalline fraction of the films was monitored by in situ electrical conductance measurements performed during isothermal annealings. The experimental conductance curves were fitted with an analytical expression, from which the characteristic crystallisation time, tc, was extracted. Using the activation energy for the growth rate extracted from our previous work, we were able to determine the activation energy for the nucleation rate for the analysed-films. For the films including small crystallites we have obtained En ∼ 2.8 eV, compared to En ∼ 3.7 eV for the completely amorphous ones.

We have fabricated polysilicon (poly-Si) thin film transistors (TFTs) using a standard 4-mask sequence, with self-aligned ion implantation for source and drain doping. The active layer was obtained by solid phase crystallisation of high purity Si2H6-deposited amorphous Si, whereas the gate oxide was synthesised by a novel plasma deposition technique, namely distributed electron cyclotron resonance plasma enhanced chemical vapour deposition (DECR PECVD). We have obtained high carrier mobilities (70 cm2V−1s−1 for electrons and 40 cm2V−1s−1 for holes) with an excellent uniformity and without the need for a post-hydrogenation treatment. Moreover, we show that the TFT characteristics are practically insensitive to hot carrier effects.

Low temperature deposition of dielectric thin films is more and more used in very largescale integrated (VLSI) circuits. For this purpose, distributed electron cyclotron resonance (DECR) plasma appears to be a promising tool. The most interesting feature of this recent plasma is the high ion density (≈1011 cm−3) associated with low electronic temperature (2–3eV) and low energy species (20–30 eV). The purpose of this study is to discuss the effects of the reactant gas mixture composition (O2sol;SiH4) and the rf substrate bias power on the physical, chemical and electrical properties of DECR SiO2 films deposited at floating temperature (<100°C). Under optimum deposition conditions, the films show excellent characteristics, comparable to those obtained with thermal oxides grown at 850–1050°C.

Conformal growth is a confined epitaxial lateral overgrowth technique capable of yielding low dislocation density GaAs films on Si. This technique makes extensive use of selective epitaxy and crystal growth is confined by a dielectric cap as well as by the self-passivated Si surface itself.

In this paper, we have performed a detailed characterisation of the state of stress of the GaAs films in various configurations (after conformal growth and removal of the seed regions, and after the regrowth of an MBE layer) by photoluminescence measurements at 5K and X-ray diffraction experiments. Although the as-grown conformal films are found in the same state of stress than reference MOCVD GaAs epilayers on Si, we report a significant decrease of this stress after MBE regrowth on conformal films.

(100) single crystal silicon films have been deposited onto (100) oriented Yttria-Stabilized Zirconia (YSZ) substrates by pyrolysis of SiH4 at ∼ 980°C.

The as deposited epitaxial silicon films have been characterized by Reflexion High Energy Electron Diffraction and Transmission Electron Microscopy techniques.

The as deposited silicon films have also been oxidized by oxygen transport through the substrate, resulting in a Si(100)/ amorphous SiO2/YSZ(100) structure in which the most defective part of the epitaxial silicon deposit has been eliminated. The oxidized interfaces (with SiO2 thicknesses in the 2000 Å range) have then been characterized by Transmission Electron Microscopy in order to assess the improvement in crystalline quality. Electrical measurements have also been performed on MOS-Hall bar structures.

We have studied the effects of pulsed laser irradiation on silicon implanted, thermally activated , Calcia Stabilized Zirconia (CSZ) capped GaAs substrates. Reference substrates have also been irradiated in air for comparison. CSZ as a solid electrolyte has been used to chemically reduce the GaAs surface native oxides prior to irradiation while maintaining the surface stoechiometry. Our results indicate a spectacular decrease in defect density after laser irradiation of the CSZ capped-native oxide free samples, as compared to the samples irradiated in air.

We have studied silicon incorporation in GaAs subsequent to Nd-YAG laser irradiation through high pressure silane atmospheres. The process involves SiH4 pyrolysis at contact with a laser-melted GaAs surface, and incorporation of the released Si atoms in the melt. SIMS analyses have allowed us to study silicon incorporation as a function of SiH4 pressure, laser energy density and number of laser shots. The high sheet resistance of the doped layers indicates that the silicon atoms are poorly electrically activated. A compensation mechanism is discussed based on oxygen penetration from native GaAs oxide layers.

Current-voltage, capacitance-voltage and defect spectroscopy techniques are used to characterize the electrical properties of GaAs crystals after pulsed laser irradiation with either a Nd-YAG or a Ruby laser. I(V) and C(V) measurements performed in conjunction on Au/GaAs Schottky structures after laser irradiation at low energy density show an important barrier lowering, of the order of 300mV. Carrier compensation up to 6×lO16/cm3 is observed in a subsurface layer whose thickness increases with deposited laser energy density. D.L.T.S. is used to study the tail of laser induced defects behind the heavily compensated layer. Finally the results are compared to those obtained following conventional thermal treatment.