Noble metal nanoparticles exhibit significant potential in all-optical, smart-sensing applications due to their unique optical properties. In particular, gold (Au) nanoparticles exhibit a strong surface plasmon resonance (SPR) band, the spectral position and shape of which depends on the size, shape, and density of the nanoparticles and the physical and chemical properties of surrounding environment. Embedding the nanoparticles in an yttria-stabilized zirconia (YSZ) matrix is believed to expand their range of operation to temperatures above 500 °C. YSZ is a material that has been proven suitable for optical applications due to its high refractive index, low absorption coefficient and high transparency in the visible and infrared regions. Thus, its use as a base platform for nanocomposite thin films is expected to provide significant benefits in the development of harsh environment multifunctional sensors.

In this work YSZ-Au nanocomposite films were synthesized from a YSZ and a Au target by the radio frequency magnetron co-sputtering technique in combination with a post-deposition annealing treatment in an argon atmosphere, with the annealing temperature being varied from 500–1000 °C in steps of 100 °C. The microstructure and the optical properties of the resulting films were characterized by x-ray diffraction spectroscopy, scanning electron microscopy and spectroscopic ellipsometry. Results on the effect of the Au particle size on the real and the imaginary part of the refractive index of the nanostructured composites are presented. Future smart sensor systems utilizing these multifunctional material sets for harsh environment sensing applications will likewise be outlined.

Ferroelectric Bi4Ti3O12 thin films were fabricated by sol-gel method with multiple rapid thermal annealing (MRTA) techniques on Pt/Ti/SiO2/p-Si substrates. The effect of annealing temperature on crystallinity, ferroelectric and electrical properties of Bi4Ti3O12 films derived by MRTA and by normal RTA were investigated. The results reveal that the grain size and the roughness of surface increase with the annealing temperature increase, but the maximal remnant polarization of Bi4Ti3O12

Thin films of BiOX, SrXTaYO, and SrXBiYTaZO (SBT) were deposited by liquid-delivery metalorganic chemical vapor deposition (MOCVD). The substrate temperature and the deposition pressure were varied from 300 to 600°C and from 0.35 to 7 mbar, respectively. Triallylbismuth (Bi-1), triphenylbismuth (Bi-2) or alkyl bismuth (Bi-3) and strontium bis-pentaethoxy-methoxyethoxy tantalate (Sr-Ta) were used as Bi precursors and as Sr-Ta precursor, respectively. X-ray photoelectron spectroscopy (XPS), ellipsometry, and scanning electron microscopy (SEM) were carried out to characterize the film properties.

The growth rates of the MOCVD of BiOX and SrXTaYO were compared to the growth rate of SBT to obtain information about mutual interaction between the precursors. The growth rate of bismuth oxide thin films deposited from Bi-1 and Bi-2 was low (∼10 nm/h at 0.35 mbar). The growth rate of strontium tantalate films was higher (up to 50 nm/h) and depended strongly on the temperature. Eight times higher (∼400 nm/h) growth rates of BiOX and SBT films were observed for the Bi-3 precursor. The deposition rate of the SBT films was quite similar to the rate of the bismuth oxide. However, the deposition rate of SBT was always lower than the deposition rate of the single Bi precursors. The growth rate significantly depended on the deposition pressure. A decrease of the deposition pressure in the reactor chamber reduced the deposition rate of BiOX, SrXTaYO, and SBT, but on the other hand, it improved the uniformity of the film thickness over the entire 150 mm wafer surface.

The XPS measurements showed a deficit of bismuth in the SBT films even though the concentration of the Bi-1 or Bi-2 precursor was several times higher compared to the Sr-Ta precursor. This problem disappeared when Bi-3 source was used.

We report in this work a Si-nanocrystal (Si-nc) MOS basic cell which shows, at the same time, fast writing times and long charge retention. This has been achieved by optimizing a structure reported previously that exhibited excellent retention characteristics. For the new structure, 15 keV Si ions have been implanted in a 40 nm thick oxide at high doses in order to obtain Si excess ranging from 10 to 20 atomic % at projected range (25nm). An annealing step at 1100 °C has been performed to precipitate the nanocrystals. We show that there is a Si excess compromise (density depth profile of Si-nc) in which write times are improved by at least 3 orders of magnitude (to the submillisecond range) while still maintaining a virtually infinite retention time. Such behavior has been correlated with structural characterization by EFTEM, which reveals a control oxide completely free of Si clusters and thick enough (11 nm) to prevent tunnelling from/to the gate electrode. The Si-ncs are located around the projected range and show a mean size of 2.7 ± 0.2 nm. The tunnel oxide is not completely free of Si-nc or clusters, as observed by EFTEM, but there is a significant reduction in mean size and density when approaching to the p-type substrate. We believe that these small Si-nc or clusters in the tunnel oxide play an important role in improving the performance of the devices. For charging (writing), when a gate bias is applied to the structure, these clusters assist like traps when tunneling to the central region. However, when the Si-nc are already charged, these nanoclusters do not similarly enhance the discharge process because they have larger band-gaps (due to quantum confinement) than the bigger Si-nc in the center of the layer, and therefore act as an insulating material. This simple model, based on the correlation of the most important electrical memory parameters and the structural information, has allowed us to engineer the implantation dose as a technological parameter when a trade-off between write and retention times is required. For our samples, this dose is about of 15% Si excess. Finally, endurance tests have been performed, showing a completely flat and stable programming window after 106 Write/Erase programming pulses.

We studied the structural and magnetic properties of dilutely (5 mol%) doped 3d elements (Co and Fe) in PLD grown HfO2 high-k dielectric thin films. Monoclinic phase of HfO2 was stabilized by Co- and Fe- substitution at significantly low growth temperature (∼725 °C). No magnetic moment was observed in Co-doped HfO2 films. On the other hand, 5 mol% Fe-doped HfO2 films grown at different oxygen partial pressures (10-6 torr to 10 mtorr) showed interesting magnetization behavior with varying coercive field due to the segregation of Fe2O3 and Fe3O4 phases. Magnetic force microscopy (MFM) study revealed magnetic impurity phase segregation. Films grown at 1 × 10-4 torr of oxygen partial pressure (O2pp) showed oriented Fe3O4 impurity line (220) and the coercive field (Hc) ∼ 350 Oe. Films grown at higher oxygen partial pressure (1x10-2 torr) showed no impurities and magnetization was absent. Coercive field varied as a function of oxygen partial pressure. This property will be of great interest from the view point of magneto-optic applications.

The silicon nanocrystal memory, that is one of the most promising devices for future non-volatile memory, is extensively investigated by experiments and simulation. The silicon nanocrystal memory cells are successfully integrated using the state-of-the-art 0.13 μm DRAM technology. The mechanism of the two-bit-per-cell operation, that is one of the unique features of silicon nanocrystal memory, is investigated and it is shown that the degree of DIBL determines the read scheme of the two-bit-per-cell operation. Moreover, the dependences of memory characteristics on device structures are examined by fabrication and measurements and it is found that the ultra-thin-body SOI and double-gate structures have better memory characteristics.

The most relevant phenomenon of this last decade in the field of semiconductor memories has been the explosive growth of the Flash memory market, driven by cellular phones and other types of electronic portable equipments (palm top, mobile PC, mp3 audio player, digital camera and so on). Moreover, in the coming years portable systems will ask even more non volatile memories either with high density and very high writing throughput for data storage application, or with fast random access for code execution in place. The strong consolidated know-how (more than ten years of experience), the flexibility and the cost make the floating gate Flash Memory a largely utilized, well-consolidated and mature technology for most of the non-volatile memory application. Today Flash sales represent a considerable amount of the overall semiconductor market.

Nowadays two of the several cell architecture proposed up to now can be considered as industry standard: the common ground NOR Flash that due to its versatility is addressing both the code and data storage segments and the NAND Flash, optimized for the data storage market.

The exploitation of the multilevel approach at each technology node allows the increase of the memory efficiency, about doubling the density at the same chip size, widening the application range and reducing the cost per bit.

In this paper the main issues related to both NOR and NAND Flash memory technology will be summarized, with the aim of describing both the basic functionality of the memory cell and the main cell architecture today consolidated. Both cells are basically a floating-gate MOS transistor, programmed by channel hot electron (NOR) or by Fowler-Nordheim tunneling (NAND) and erased by Fowler-Nordheim tunnel. The main reliability properties, charge retention and endurance, are presented, together with some comments on the basic physical mechanisms responsible for.

A couple of innovative approaches to floating gate cell evolution, namely nanocrystal memory and 3-D cell will be described.

Finally the Flash cell scaling issues will be covered, pointing out the main challenges. The Flash cell scaling has been demonstrated to be really possible and to be able to follow the Moore's law down to the 90 nm technology generations. The technology development and the consolidated know-how are expected to sustain the scaling trend down to the 50 nm technology node and below as forecasted by the ITRS roadmap.

We present an all-organic permanent memory transistor using an amorphous spin-cast gate insulator. This gate insulator exhibits a remanent polarisation in its amorphous state, a unique property, which is best described as “ferroelectric-like”. The memory transistor thus built perform extremely well, even when compared to inorganic ferroelectric memory transistors; the memory “on” to memory “off” current ratio is close to 3×10-a4, while time-dependent studies show retention times of 14 hours and more.

We have studied capacitance-voltage (C-V) and displacement current-voltage characteristics of MOS capacitors with Si nanocrystals embedded in the gate oxide as a floating gate in dark and under visible light illumination at room temperature to gain a better understanding of discrete charged states of the Si-dots floating gate. The Si-dots floating gate with a dot density of 2.8×1011cm-2 and an average dot size of 8nm was fabricated on ∼2.8nm-thick thermally-grown SiO2 as a tunnel oxide by the thermal decomposition of SiH4, and covered with 7.5nm-thick control oxide prepared by thermal oxidation of a-Si. C-V characteristics of Al-gate MOS capacitors on p-type and n-type Si(100) show unique hystereses due to the charging and discharging of the Si-dots floating gate with a symmetric pattern reflecting the Fermi level of the substrate, which enable us to rule out the contribution of traps with a specific energy state to the observed hystereses. For each of high-frequency C-V curves measured in dark, a single capacitance peak appears only around a flat-band voltage condition, which is attributed to the quick flat-band voltage shift caused by the collective emission of charges retaining in the Si-dots floating gate as confirmed from the corresponding displacement current peak. Under visible light illumination, another capacitance peak due to collective charge injection to the electrically neutral Si-dots floating gate becomes observable in the inversion condition governing the on-state of MOS FETs. Thus, the optimum bias conditions for dot-floating gate MOSFETs can be predicted from the capacitor characteristics measured under light illumination.

It expected that for many years to come, the majority of the nonvolatile memories shipped will be based on current mainstream flash technologies, which utilize transistor based charge storage memory cells and multi-level-cell concepts, for storing more than one logic bit in a single physical cell. Moore's law will continue to drive transistor based memory technology scaling but technology complexity will be increasing. In order to meet technology scaling, the mainstream transistor based flash technologies will start evolving to incorporate material and structural innovations. This paper will review the current status and discuss the approaches being explored to provide scaling solutions for future transistor based non-volatile memory products. Based on the introduction of material innovations, it is expected that the planar transistor based flash memory cell can scale into the 32nm node. Further, more complex, structural innovations will be required to maintain further scaling. New memory concepts, not relying on transistors as a basis of the memory cell, provide new opportunities for future low cost memories. Several of these new concepts will be summarized and contrasted with the mainstream transistor based flash memory technologies.

Flash memories are now widely spread and conveniently used in mobile devices such as cellular phones, pagers, PDAs (Personal Digital Assistants), digital cameras and so on. And in the coming ubiquitous era, nonvolatile solid-state memories are expected to be more and more important for these mobile devices. However, Flash memories are not perfectly suitable for these mobile devices since their power consumptions are too high, writing speeds are two slow, programming endurances are limited up to 106 cycles. To resolve these problems, numbers of new nonvolatile solid-state memories are proposed and some of them are now under development. Among these newly emerging nonvolatile memories, FeRAMs (Ferroelectric Random Access Memories) are the only ones that are now in production. However, the process and materials to produce FeRAMs have not matured yet to support the ubiquitous technologies.

In this study, we explore the process technologies and materials required for the future FeRAMs and obtained the result that the requirements can be satisfied by the known technologies at present.

A 4Mb magnetoresistive random access memory (MRAM) with a novel magnetic free layer and toggle switching mode is presented. The new free layer uses a balanced synthetic-antiferromagnet trilayer structure and a novel write pulse sequence to provide robust switching performance with immunity from ½-select disturbs. This new mode greatly improves the switching performance of the MRAM as compared to conventional MRAM. The intrinsic reliability of the magnetoresistive tunnel junction (MTJ) and the metal interconnect system of MRAM are two other areas of great interest due to the new materials involved. Time dependent dielectric breakdown (TDDB) and resistance drift were the two main failure mechanisms identified for intrinsic memory bit reliability. Results indicated that a lifetime over 10 years is achievable under the operating conditions. Finally data retention is demonstrated over times that are orders of magnitude longer than 10 years.

Rare-earth-substituted tetragonal lead zirconate titanate thin films were synthesized for improving the ferroelectric property of conventional lead zirconate titanate. Thin films of Pb1.00REx (Zr0.40Ti0.60)1-(3x /4)O3 (x = 0.02, RE = Y, Dy, Er and Yb) were deposited on (111)Pt/Ti/SiO2/(100)Si substrates by a chemical solution deposition (CSD). B-site substitution using rare-earth cations described above enhanced the crystal anisotropy, i.e., ratio of PZT lattice parameters c/a. Remanent polarization (Pr) of PZT film was enhanced by Y3+-, Dy3+- and Er3+-substitution from 20 μC/cm2 up to 26, 25 and 26 μC/cm2 respectively, while ion substitution using Yb3+ degraded the Pr value down to 16 μC/cm2. These films had similar coercive fields (Ec) of around 100 kV/cm. Improving the ferroelectric property of PZT film by rare-earth-substitution would be ascribed to the enhancement of the crystal anisotropy. We concluded that ion substitution using some rare-earth cations, such as Y3+, Dy3+ or Er3+, is one of promising technique for improving the ferroelectric property of PZT film.