Hostname: page-component-76fb5796d-dfsvx Total loading time: 0 Render date: 2024-04-26T04:29:08.847Z Has data issue: false hasContentIssue false
  • English
  • Français

Non Volatile Memory Technologies: Floating Gate Concept Evolution

Published online by Cambridge University Press:  01 February 2011

Cesare Clementi  and
Roberto Bez
Cesare Clementi
Affiliation:
Central R&D – Non Volatile Memory Technology Development, STMicroelectronics, Via C. Olivetti 2, 20041 Agrate Brianza (MI) -, Italy
Get access

Abstract

The most relevant phenomenon of this last decade in the field of semiconductor memories has been the explosive growth of the Flash memory market, driven by cellular phones and other types of electronic portable equipments (palm top, mobile PC, mp3 audio player, digital camera and so on). Moreover, in the coming years portable systems will ask even more non volatile memories either with high density and very high writing throughput for data storage application, or with fast random access for code execution in place. The strong consolidated know-how (more than ten years of experience), the flexibility and the cost make the floating gate Flash Memory a largely utilized, well-consolidated and mature technology for most of the non-volatile memory application. Today Flash sales represent a considerable amount of the overall semiconductor market.

Nowadays two of the several cell architecture proposed up to now can be considered as industry standard: the common ground NOR Flash that due to its versatility is addressing both the code and data storage segments and the NAND Flash, optimized for the data storage market.

The exploitation of the multilevel approach at each technology node allows the increase of the memory efficiency, about doubling the density at the same chip size, widening the application range and reducing the cost per bit.

In this paper the main issues related to both NOR and NAND Flash memory technology will be summarized, with the aim of describing both the basic functionality of the memory cell and the main cell architecture today consolidated. Both cells are basically a floating-gate MOS transistor, programmed by channel hot electron (NOR) or by Fowler-Nordheim tunneling (NAND) and erased by Fowler-Nordheim tunnel. The main reliability properties, charge retention and endurance, are presented, together with some comments on the basic physical mechanisms responsible for.

A couple of innovative approaches to floating gate cell evolution, namely nanocrystal memory and 3-D cell will be described.

Finally the Flash cell scaling issues will be covered, pointing out the main challenges. The Flash cell scaling has been demonstrated to be really possible and to be able to follow the Moore's law down to the 90 nm technology generations. The technology development and the consolidated know-how are expected to sustain the scaling trend down to the 50 nm technology node and below as forecasted by the ITRS roadmap.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 830: Symposium D – Materials and Processes for Nonvolatile Memories , 2004 , D1.2
Copyright
Copyright © Materials Research Society 2005

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. “Semiconductor Industry Outlook: 2002 NVM Conference”, Webfeetb inc. Report, 2002 Google Scholar
2. Lai, S., “Flash memories: where we were and where we are going”, IEDM Tech Dig, p.971, 1998 Google Scholar
3. Pavan, P., Bez, R., Olivo, P., Zanoni, E., “Flash memory cells – An overview”, Proc of the IEEE, 85, p.1248, 1997 Google Scholar
4. Pavan, P., Bez, R., “The industry standard Flash memory cell”, in “Flash Memories” edited by Cappelletti, P. et al., Kluwer Academic Publishers, 1999 Google Scholar
5. Masuoka, F., Momodomi, M., Iwata, Y., Shirota, R., “New ultra high density EPROM and Flash with NAND structure cell”, IEDM Tech. Dig., p.552, 1987 Google Scholar
6. Aritome, S., “Advanced Flash Memory technology and trends for file storage application”, IEDM Tech Dig., session 33, 2000 Google Scholar
7. Selmi, L., Fiegna, C., “Physical aspects of cell operation and reliability” in “Flash Memories” edited by Cappelletti, P. et al., Kluwer Academic Publishers, 1999 Google Scholar
8. Ricco', B. et al., Proc. IEEE, 86, 2399 (1998)Google Scholar
9. Cappelletti, P., Bez, R., Cantarelli, D., Fratin, L., “Failure mechanisms of Flash cell in program/erase cycling”, IEDM Tech. Dig., p.291, 1994 Google Scholar
10. Crisenza, G., Ghidini, G., Manzini, S., Modelli, A., Tosi, M., “Charge loss in EPROM due to ion generation and transport in interlevel dielectrics”, IEDM Tech. Dig., p.107, 1990 Google Scholar
11. Crisenza, G., Clementi, C., Ghidini, G., Tosi, M., “Floating gate memories”, Quality and Reliability Engineering International, 8, p.177, 1992 Google Scholar
12. International Technology Roadmap for Semiconductors, 2003 EditionGoogle Scholar
13. Ichige, M. et al., “A novel self-aligned shallow trench isolation cell for 90 nm 4 Gbit NAND Flash EEPROMs”, 2003 Symp. On VLSI Technology Digest Google Scholar
14. Blomme P. et al., “A novel low voltage memory device with an Engineered SiO2/High-k tunneling barrier”, NVSMW Digest 2003 Google Scholar
15. Muralidhar, R. et al., “A 6V Embedded 90 nm Silicon Nanocrystal Non Volatile memory”, IEDM Tech. Dig., p.601, 2003 Google Scholar
16. De Salvo, B. et al., “How far will Silicon nanocrystals push the scaling limits of NVM technologies?”, IEDM Tech. Dig., p.597, 2003 Google Scholar
17. Fazio, A., “Flash Memory Scaling”, MRS Bulletin, November 2004, pg. 814–817 Google Scholar