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Integration and Performance Improvements of Silicon Nanocrystal Memories

Published online by Cambridge University Press:  01 February 2011

T. Hiramoto ,
I. Kim ,
M. Saitoh  and
K. Yanagidaira
T. Hiramoto
Affiliation:
Institute of Industrial Science, University of Tokyo 4–6–1 Komaba, Meguro-ku, Tokyo 153–8505, Japan
I. Kim
Affiliation:
Institute of Industrial Science, University of Tokyo 4–6–1 Komaba, Meguro-ku, Tokyo 153–8505, Japan
M. Saitoh
Affiliation:
Institute of Industrial Science, University of Tokyo 4–6–1 Komaba, Meguro-ku, Tokyo 153–8505, Japan
K. Yanagidaira
Affiliation:
Institute of Industrial Science, University of Tokyo 4–6–1 Komaba, Meguro-ku, Tokyo 153–8505, Japan
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Abstract

The silicon nanocrystal memory, that is one of the most promising devices for future non-volatile memory, is extensively investigated by experiments and simulation. The silicon nanocrystal memory cells are successfully integrated using the state-of-the-art 0.13 μm DRAM technology. The mechanism of the two-bit-per-cell operation, that is one of the unique features of silicon nanocrystal memory, is investigated and it is shown that the degree of DIBL determines the read scheme of the two-bit-per-cell operation. Moreover, the dependences of memory characteristics on device structures are examined by fabrication and measurements and it is found that the ultra-thin-body SOI and double-gate structures have better memory characteristics.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 830: Symposium D – Materials and Processes for Nonvolatile Memories , 2004 , D1.5
Copyright
Copyright © Materials Research Society 2005

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References

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