It is known that the interface between a refractory metal barrier and a dielectric material is stable against thermal treatment at a conventional IC interconnect processing temperature. However, the interface may not be stable against thermal and electrical stress called the bias temperature stress (BTS) at moderate conditions of 150 °C and 0.5 MV/cm. Massive refractory metal ions are seen to drift into low K dielectric materials that contain a mixture of organic and inorganic elements. It is argued that the oxidation of the metal at the interface creates unstable metal ions that are ready to drift into the dielectric film under an electric filed during the BTS test. Dielectric or dielectric capping materials that do not contain oxygen can prevent metal oxidation and are desirable to create a stable metal and dielectric interface.

Based on the theory of superhydrophobicity for low surface energy coatings, we describe a superhydrophobic antistiction silica coating for MEMS devices. The process uses a novel sol-gel process sequence with a eutectic liquid as a templating agent. The eutectic liquid displays negligible vapor pressure and very low melting point (12°C at ambient conditions) to reduce solvent loss during the high speed spincoating process. After a fluoroalkyl silane treatment, superhydrophobicity is achieved on the as-prepared silica thin film. The solvent can be extracted after the gelation and aging processes. Spin speed effect, eutectic liquid:TEOS ratio in the solution were studied in order to optimize the surface roughness to ensure excellent super-hydrophobicity. Comparison of the silica thin films with silicon pillar surfaces showed that superhydrophobicity for the traditional sol-gel derived silica films demonstrated significant improvement, especially under humid conditions. The AFM force curve obtained with a tipless probe showed that the interaction force is greatly reduced on a rough silica superhydrophobic surface. This result offers great potential to reduce stiction failures in MEMS devices.

Atomic layer deposition (ALD) of ultra-thin barrier layers is a key process for implementation of Cu/low k interconnects. Low k dielectric surfaces are generally characterized by weak surface bonds which have to be properly activated for barrier formation. In this study, we investigated the surface activation of low k dielectrics by atomic hydrogen, nitrogen and ammonia beams for ALD of Ta/TaN barrier layers. In-situ x-ray photoemiision spectroscopy (XPS) together with differential FTIR were used to examine the beam modification of the surface and the subsequent growth on the low k surface. The evolution of the low k surface chemistry revealed an initial transient growth region controlled mainly by the substrate surface chemistry. The initial chemisorption was found to be through formation of Ta-O bonds on organosilicates (OSG) and charge transfer complexes on aromatic SiLK. This led to a significant slower initial nucleation on the OSG low k surface without beam activation. The atomic beams, particularly the nitrogen and amine radials, were found to serve as effective reducing agents in initiating and enhancing the precursor chemisorption. This led to an improvement of the barrier film quality and an increase of the deposition rate at a temperature compatible with low k dielectrics (< 400C). In the subsequent linear growth region, atomic hydrogen species was able to reduce the chlorine content under appropriate temperature and with sufficient purge. The effect of porosity in low k dielectrics on barrier formation will be discussed.

Elevated bonding temperature for interconnection deteriorates the reliability of both the device and the interconnect; hence the imperative for developing low temperature bonding methods. This study investigates the feasibility of using self-assembled monolayers (SAMs) to assist direct gold-gold bonding. This involves a simple molecular self-assembly process whereby a monolayer of alkyl chains with a sulfur end group is attached to the gold surface prior to thermocompression bonding. Using this method, we have achieved gold to gold bonding at a bonding temperature below 100°C, a significant reduction compared to the conventional bonding temperatures of above 150 °C. We attribute this temperature reduction to two properties of SAMs - (1) surface passivation of the Au surface that precludes adsorption of surface contaminants, and (2) The easy displacement of SAMs through thermal desorption just before bonding occurs. This SAMs-assisted bonding mechanism is supported by X-ray photoelectron spectroscopy (XPS) and surface plasmon resonance (SPR) results.

Chemical vapor deposition (CVD) of copper using both a novel Cu(II) β-diketonate source and hydrogen reduction process was studied to fill contact vias with the smallest diameter in the 32nm and more advanced generation chip. Pure Cu films were grown under the condition with the product of hydrogen partial pressure and H2/Cu source molar ratio being over 1,000,000. We succeeded in filling the 40-nm-diameter contact vias by optimizing the growth condition of the Cu-CVD in both substrate temperatures and reaction pressures.

The industry trend towards smaller feature size and higher integration density leads to multi-level Cu/low-k interconnect schemes with reduced line width and spacing. Mechanical stress is generated during interconnect fabrication. The spatial distribution of the stress is strongly affected by the layout variation. The packaging process generates a global chip level stress that permeates to the local interconnect level. Stress related failures and yield loss are major areas of concern for Cu/low-k interconnects. The effects of fabrication process, layout variation, and packaging process on the final stress distributions in Cu/low-k interconnect structures are examined and the reliability impact of mechanical stress is assessed.

A new mechanical stress characterization method has been developed for Damascene copper interconnects. The micro strain gauge based on a rotating beam has been fabricated in situ on a standard industrial CMOS production line. Comparison of the beam deviation in the fabricated sensor with usual geometrical model is discussed. The saturation of the beam deviation leads to an analytical model which takes the stiffness of the anchoring points into account. This model gives a direct value of the local stress in the copper line for different annealing times. We show that this value is different from the one given by a curvature measurement method. The microstructure of the Damascene copper induces a higher stress level than full sheet deposition copper. The sensor was developed to be compatible within a CMOS process. It is suitable for in situ mechanical stress monitoring in Damascene lines and process optimization.

Adhesion strength of the interface between Cu film and SiCN cap layer for IC metallization system was evaluated by a technique developed by the authors. In this technique, microscopic specimens with the in-plane dimension less than 10 μm were fabricated by focused ion beam system and loaded directly by a sharp diamond stylus with submicron tip radius. By comparing the crack extension behavior with the three-dimensional numerical simulation, the interface adhesion energy was evaluated to be 5 J/m2. The same interface was subjected also to the four-point bending experiment, which is widely applied to interface adhesion measurement. The evaluation results by the two techniques agreed reasonably well with each other.

The deposition and post-treatment processes involved in the production of porous organosilicate glasses (OSGs) by plasma-enhanced chemical vapor deposition (PECVD) with ultraviolet light (UV) treatment are investigated through the use of a deuterated organic porogen precursor using infrared spectroscopy and solid-state nuclear magnetic resonance spectroscopy. Infrared analysis provides evidence for hydrogen-deuterium scrambling between the chemical species during the deposition process, which is exacerbated by the UV treatment process. Analysis of 13C cross-polarized magic angle spinning (CP-MAS) NMR suggests that the porogen exists in domains relatively isolated from the network, in agreement with short UV treatment time morphological data that indicates the pore size is relatively constant from the early stages of UV treatment process. The chemical and morphological information provides further support for a deposition controlled morphology and has implications towards enhanced chemical processing of porous organosilicate glass (OSG) films for back-end-of-line integrated circuit manufacturing.

A novel technique that combines laser thermoreflectance measurement with the 3-omega method is proposed for evaluating the heat capacity of low-k films and the heat resistance at the interface between the low-k film and Si substrate. It was demonstrated that the heat capacity of thin films and the heat resistance at the interface can be determined by obtaining the heat effusivity of the film from laser thermoreflectance measurements, the total heat resistance obtained with the 3-omerga method, and the film density and thickness found from x-ray reflectivity measurements. The heat capacity of SiOC films was determined to be Cp(SiOC) =1.1 kJ/kgK with interface heat resistance of Rint(SiOC) = -2.37×10−8 m2k/W, while the heat capacity of Th-ox films was determined to be Cp(Th−ox) =0.61 kJ/kgK with Rint(Th−ox) = +1.74×10−8 m2k/W. A DSC heat capacity measurement confirmed the reliability of the evaluated Cp data. XRR and TEM examinations revealed that the negative interface heat resistance exhibited by the SiOC films originated from a high density layer at the interface between the film and Si substrate; and the positive interface heat resistance displayed by the Th-ox films stemmed from atomic defects at the interface between the film and Si substrate. These results confirmed that this method is a reliable and effective method for evaluating the heat capacity of low-k films and the heat resistance at the interface.

The thermal stability of Ag(Cu) alloy thin films on indium tin oxide (ITO) has been investigated and compared to that of pure Ag thin films on ITO. Atomic force microscopy and X-ray diffraction results of annealed films show differences in the evolution of surface morphology and texture with annealing. The presence of Cu atoms in the silver impacts the surface energy and surface diffusion. This results in Ag and Ag(Cu) alloy having very different surface morphology and crystallographic texture. The enhanced texture and thermal stability of the Ag(Cu) alloy constitute its potential use contact as material for MOSFET and for flip-chip light-emitting diodes.

Grain growth in polycrystalline films is controlled by the energetics of the surface, interface and grain boundaries as well as strain energy. The unique character of damascene lines fabricated from electroplated Cu films introduces the additional considerations of bath chemistry and geometric constraints. The moderate stacking fault energy of Cu allows for the development of a substantial twin fraction for certain growth conditions. This paper discusses in-situ observation of grain growth in Cu films and lines under various processing conditions. It is shown that for thicker films and for structures constrained within damascene trenches the energetics of twin boundary formation play a large role in texture development of these structures.

We report on recent progress in the directed self-assembly of discrete inorganic semiconductor device components. Different from prior research, the goal is to enable the integration of increasingly small dies while supporting unique-angle orientation and contact pad registration. The process is based on the reduction of surface free energy between liquid solder coated areas on the substrate and metal-coated binding sites on the semiconductor dies. Recent advances include flip-chip assembly with unique angular orientation accomplished using “two-element” docking sites that contain pedestals that act as chaperones for the solder directed assembly to take place. The scale reduction to 20 μm sized components involves the use of a liquid-liquid interface to concentrate component delivery and speed up the self-assembly process to prevent oxidative dissolution of the solder sites prior to completion.

In this study, a novel method is explored for improving the electromigration lifetime of Cu wires, using Ta implantation into Cu. For high implant doses (2E15 cm−2), the electromigration lifetime is improved by over 5X using this method. An increase in lifetime is achieved, even for an average surface concentration of Ta on the order of 0.1 atm%. We propose that the improvement in electromigration lifetime is due to the reduction of defects at the SiN/Cu interface due to the presence of Ta. The line-to-line leakage at high voltages (> 5V) increases with the Ta implant, with higher leakage at higher Ta concentrations, so the Ta dose must be limited to avoid excessive leakage.

In this paper, low temperature amorphous silicon oxynitride (a-SixOyNz:H) thin film technology is proposed for implementation of CMOS compatible photonic crystal (PC) based optical integrated circuits (OICs). The a-SixOyNz films of different refractive indices were developed by plasma enhanced chemical vapor deposition (PECVD) technique using silane, nitrous oxide, and ammonia as gas phase precursors at 300°C. The films with refractive index between 1.43 − 1.75 were obtained by changing gas flow ratios. Such thin films can be used as cladding and core layers in photonic crystal structure.

The bandgap and guiding properties of the a-SixOyNz based PCs were simulated and was shown that the a-SixOyNz:H based PC technology offers larger feature sizes than a conventional silicon based photonic crystals.

Bump process using gold bump led to many cleaning problems like polymer residues, metal and polyimide consumption after stripping process. First of all, stripping process of bump photoresist is one of the difficult technologies since thickness of PR pattern of bump is thicker than that of general metal line at least 100 times. We investigated the improvement of LDI BUMP stripping Process at 25 with new chemical. We found that the wettability may be improved when the additive was added to the chemical and it improves the stripping ability. It was found that new chemical was superior to commercial chemical in terms of chemical stability, removal efficiency of polymer residue and decrease in metal and polyimide consumption. Also, we could obtain removal mechanism of photoresist pattern by measured Raman equipment and enhancement of yield in mass production line of semiconductor.

This paper describes process optimization of UV curing for ultra Low-k SiOC (ULK-SiOC, k=2.65) and High stress silicon nitride (HS-SiN) liner. We have investigated the impact of UV curing using different UV bulbs (UV-X and UV-Y) on BEOL process damages to the ULK-SiOC. The k-value variations of ULK-SiOC modified with UV-X with higher photon energy than UV-Y are greater than those of the pristine ULK-SiOC and the ULK-SiOC modified with UV-Y. These results are consistent with the previously reported FT-IR and NMR analyses that the UV-X generates 3-fold Si-O ring defects and Si-H bonds in the ULK-SiOC. In order to discuss the pore structure in UV-modified ULK-SiOC, the solvent diffusion of toluene and ethanol in ULK-SiOC were measured. The solvent diffusion of the UV-modified ULK-SiOC with UV-X is faster than that of the UV-modified ULK-SiOC with UV-Y. This result indicates that the pore size of UV-modified ULK-SiOC with UV-X is larger than that of UV- modified ULK-SiOC with UV-Y. The dependence of the stress increase in HS-SiN liner on different UV bulbs (UV-X and UV-Y) has been investigated by using stress measurement and FT-IR. The UV-modified HS-SiN liner with UV-Y achieves higher tensile stress, compared to the UV-X. FT-IR results have revealed that UV-Y is more effective for the dehydrogenation and SiN crosslinking, resulting in the greater increase in the tensile stress. In conclusion, UV-Y bulb with medium photon energy yields the desired UV modifications for ULK-SiOC and HS-SiN applications.

Reliability is an important requirement for the newly developed porous low-k ILD materials that are being introduced into (BEOL). Dependence of Young's moduli, as measured by nanoindentation technique, on the environment [such as high relative humidity, water immersion and recovery] is presented along with FT-IR spectra for a number of films with different k values. Effect of the moduli changes on cracking behavior is also discussed.

The increase of integrated circuits performances requires ultra-low dielectric constant (ULK) materials to minimize the drawbacks of miniaturization. Amorphous SiOCH are promising candidates for ULK materials as porosity can be introduced via a two steps elaboration. In a first step, organo-silicon species and organic species are co-deposited by PECVD. Then, a thermal annealing, alone or assisted by UV radiation, removes the organic labile phase and creates pore inclusions into the final material. In this work, the extendibility of this porogen approach is investigated in order to lower the dielectric constant. An increase of the porogen loading in hybrid film is studied by tuning the precursors ratio injected in the plasma gas feed. The increase of organic species amount is operated in order to create more pores sites. However, the post-treatment does not lead automatically to higher porosity. Actually, an increase of the porosity is observed only until a porogen loading limit and decreases above this limit. The shrinkage of the film during the post-treatment can explain this limitation. For high ratios of porogen, the film shrinkage increases drastically and leads to a decrease of the porosity finally created. At last, the link between porosity and dielectric constant is enlightened and a minimum in term of K value is reached with both post-treatments: dielectric constant of 2.1 and 2.3 are obtained using respectively thermal treatment and UV curing.

The AC fatigue test technique, which uses cyclic joule heating to apply thermal cycles to thin-film structures, was applied to copper lines and vias in damascene dielectric structures on silicon substrates. Specimen chips with two different types of dielectric, oxide and low-k, were tested. The lines were 300 nm wide; various via widths were tested. At 100 Hz, cyclic temperature ranges from 400 to 900 °C produced line lifetimes between 10 and 1 million seconds. Similar lifetimes were reached in the vias for temperature ranges between 100 and 500 °C. The data were plotted as number of load reversals to failure against cyclic temperature range; the data trends for the two different types of dielectric were indistinguishable. When the line data were fit to the Basquin equation for mechanical fatigue, the temperature ranges for both dielectrics at the one1-reversal intercept were above 1000 °C. The via data were more scattered, but trended toward a lower intercept temperature.