In this study, we propose a novel cooling scheme that utilizes copper inverse opals (CIOs) for surface enhancement in a single-phase impingement jet cooling system. We perform computational fluid dynamics simulations to evaluate the cooling performance of the CIO jet coolers. Our modelling results indicate that the proposed CIO-coated cooler can significantly reduce the average temperature and improve the temperature uniformity across the entire chip surface. The average Nusselt number of the CIO-coated cooler can reach up to 2.8 times that of the flat surface jet cooler. However, the porous structure of the CIO-coated cooler increases the total pressure drop. To determine designs with high cooling performance and low energy consumption, we investigate two crucial design factors, namely the inlet velocity and the nozzle-to-CIO distance. Our analysis reveals that increasing the inlet velocity further enhances the heat transfer, but at the expense of high pressure drop. On the other hand, a larger nozzle-to-CIO distance results in a lower pressure drop but also reduces the heat transfer coefficient. The effects of nozzle-to-CIO distance are further understood by studying the flow resistance network. Furthermore, we present a reduced-order model that accurately captures the thermofluidic characteristics of the proposed design.

Formulated, processed, and dried Aloe polysaccharides thin film sandwiched between ITO as bottom electrode and Au as top electrode has been adopted as an artificial synapse to emulate behavior of neuromorphic computing. The synaptic plasticity or weight has been modulated with this simple metal-insulator-metal structure by applying voltage sweep and voltage pulse, with excitatory postsynaptic current being monitored. Synaptic potentiation and depression has been demonstrated by applying 6 consecutive sweeps of voltage in positive and negative polarity, respectively. By varying number (10 – 50) of voltage pulses, variable synaptic weight has been measured with paired pulse facilitation and post-tetanic potentiation indexes of 2.61x10-6and 1.45x10-4, respectively. The short-term plasticity and long-term potentiation can be clearly revealed when applying 40 pulses and beyond, with extracted time constants of approximately 28 s at 40 pulses and 90 s at 50 pulses.

Capacitors represent the largest obstacle to dynamic random-access memory (DRAM) technology evolution because the capacitor properties govern the overall operational characteristics of DRAM devices. Moreover, only the atomic layer deposition (ALD) technique is used for the dielectric and electrode because of its extreme geometry. Various high-k materials deposited by ALD have been investigated for further scaling. Whereas past investigations focused on increasing the physical thickness of the dielectric to suppress leakage current, the physical thickness of the dielectric should also be limited to a few nanometers in design rules less than 1×-nm. Therefore, a new way to overcome the limitations of traditional approaches based on thorough understanding of high-k materials is highly recommended to enhance the properties of conventional materials and provide directions for developing new materials. In this review, previously reported results are discussed, and suggestions are made for further investigations for DRAM capacitor applications.

High-current switching performance of ovonic threshold switching (OTS) selectors have successfully enabled the commercialization of high-density three-dimensional (3D) stackable phase-change memory in Intel’s 3D Xpoint technology. This bridges the huge performance gap between dynamic random access memory (DRAM) and Flash. Similar to phase-change memory, OTS uses chalcogenide-based materials, but whereas phase-change memory reversibly switches between a high-resistance amorphous phase and a low-resistance crystalline phase, OTS freezes in the amorphous phase. In this article, we review recent developments in OTS materials and their performance in devices, especially current density and selectivity. Advantages and challenges of OTS devices in the integration with the phase-change memory are discussed. We introduce the evolution of theoretical models for explaining the OTS behavior, including thermal runaway, field-induced nucleation, and generation/recombination of charge carriers.

Using ab initio simulation, we study a ferroelectric layer of a few nanometers made of hafnia (HfO2) under the influence of Si doping with TiN electrodes. We evaluate the orthorhombic phase of Pca21 symmetry, its ferroelectric switching and the incidence of doping with silicon. We show that the ferroelectric switching can involve a 90° characteristic angle with corresponding activation energy which is lowered by a factor three due to Si doping at 3% at. A full MFM (Metal-Ferroelectric-Metal) model is derived in order to simulate finite-size effects. This model is compatible with a reversal of a polar HfO2:Si with a (111) preferential orientation. Validity and usefulness of such a model are discussed for ferroelectric devices optimization.

Organic light-emitting diodes (OLEDs) have attracted huge concern because of their intrinsic characteristics and ability to reach the pinnacle in the field of high-quality flat-panel displays and energy-efficient solid-state lighting. High-efficiency is always a key crux for OLED devices being energy-saving and longer life-span. OLEDs have encountered enormous difficulties in meeting the requirements for large-sized devices due to a major limitation in vacuum thermal evaporation technology. In multilayered OLED devices, the characteristics of the charge injection/transport layer is a crucial factor for the operating-voltage, power-efficiency and stability of the device. Transition metal oxides have shown great potential owing to their wide range of possible energy level alignments, balanced charge injection, and improvement of carrier mobilities. In this study, we report a solution-processed blend V2O5-PEDOT:PSS hole-injection/hole-transport layer (HIL/HTL) for efficient orange phosphorescent OLEDs. The electroluminescent characteristics of blend V2O5-PEDOT:PSS based devices were studied with the structure ITO/V2O5-PEDOT:PSS/CBP:Ir(2-phq)3/TPBi/LiF/Al. The V2O5-PEDOT:PSS based OLEDs displayed relatively higher device performance and low roll-off than that of the counter PEDOT:PSS device in terms of a maximum luminance of 17,670 cd m-2, power efficiency of 19.4 lm W-1, external quantum efficiency of 8.7%, and more importantly, low turn-on voltage. These results demonstrate an alternative approach based on metal oxide/organic blend HIL/HTL as a substitute of PEDOT:PSS for high-efficiency solution process OLEDs.

The patterning of gold and silver micro and nanostructures on rigid and flexible substrates is investigated by microcontact printed thiol based self-assembled monolayers. The aspect ratio of the noble metal micro and nanostructures is determined by interaction of the -SH head group of the CH3(CH2)19SH molecules and the surface of the noble metal. Silver micro and nanostructures with >10 times higher aspect ratios can be realized in comparison to commonly realized gold micro and nanostructures. The printing process is described, and the etching process is characterized in terms of etching window and etching selectivity. Potential electronic and photonic applications of the micro and nanostructures are discussed taking the boundary conditions of the printing process and the selected material system into consideration.

Frequent switching of resistive memory cell may lead to a local accumulation of Joules heat in the device. Since the ReRAM cells are arranged in crossbar arrays with the two electrodes running perpendicular to each other, the heat generated in one device spreads via common electrode metal lines to the neighboring cells causing their performance degradation. Also cells that do not share any of the two electrodes (e.g. the diagonal array cells) with the hot device may also degrade provided the intermediate cells are set to an on-state establishing thus a continuous thermal conduction path between the heated and the probed device. It is found that the heat conduction along the active Cu electrode is more pronounced than that along the inert Pt electrode. Devices with Rh inert electrode performed better than those with Pt electrode due to better heat conductivity properties of Rh vs Pt. The heat dissipation is also found worse for a heated device with narrow and thin lines causing, however less degradation of more distant neighbor cells than for wide and thick metal lines. Finally, there is a trade-off between dissipating the heat quickly form the heated device to increase its maximum switching cycles and the heat exposure of the neighboring devices.

This paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and random accessed magnetic devices. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of only one transistor (MOSFET) – small size, and more cost effective, compared with a 6-Transistor SRAM. There is no need to refresh, as required by DRAM. The access time can be less than 1ns – close to the speed level of relaxation time - much faster than traditional FLASH memories and comparable to volatile DRAM. The operating voltages for all memory functions can be as low as high speed CMOS.

Substantial increase of output current, and Ion / Ioff ratio for sub-7nm low power CMOS transistors, can be accomplished using a novel optoelectronic technology, which is 100% compatible with existing CMOS process flow. For RF or mixed signal ASICs, adding photonic components may improve the cut-off frequency, and reduce series resistance. Products that utilize power regulating devices, such as power MOSFETs, will benefit from the optoelectronic configuration to achieve much lower Rdson and high voltage at the same time. For semiconductor memories, such as DRAM or FLASH, the photonic technique may reduce the ERASE / WRITE / access time and improve the reliability.

In this paper we report high voltage MOS and Schottky Diode CV techniques for silicon and SiC power devices. 4H Silicon carbide is a wide bandgap semiconductor suitable for high voltage power electronics and RF applications due to high avalanche breakdown critical electric field, and thermal conductivity. The performance of various power devices, which may include MOSFET and Static Induction Transistor (SIT), can be affected by the deep level traps in the substrate and the oxide interfacial defects. We have characterized deep level trap (High Voltage Schottky Diode HF CV) and oxide interface trap densities (High Voltage HF MOS CV), measured the device channel doping profile for both 4H SiC and silicon, gate metal workfunction, and simulated the effects on DC/AC performance.

This article focuses on the finite element modeling of toroidal microinductors, employing first-of-its-kind nanocomposite magnetic core material and superparamagnetic iron nanoparticles covalently cross-linked in an epoxy network. Energy loss mechanisms in existing inductor core materials are covered as well as discussions on how this novel core material eliminates them providing a path toward realizing these low form factor devices. Designs for both a 2 μH output and a 500 nH input microinductor are created via the model for a high-performance buck converter. Both modeled inductors have 50 wire turns, less than 1 cm3 form factors, less than 1 Ω AC resistance, and quality factors, Q’s, of 27 at 1 MHz. In addition, the output microinductor is calculated to have an average output power of 7 W and a power density of 3.9 kW/in3 by modeling with the 1st generation iron nanocomposite core material.

This article reviews a grounding in thin-film science and technology, an interest in combining materials science with applied physics and electrical engineering, and the active pursuit of collaborations with experts in other disciplines. That basis has enabled participation in the beginnings of integrated-circuit technology, the invention of new solar cells, the understanding of hydrogenated amorphous silicon for solar cells and thin-film transistors, the development of the principles of flexible, conformable, and stretchable electronics, and the devising and demonstration of large-area electronic systems.

Lorentz reciprocity governs the symmetry with which electromagnetic signals travel in space and time. A reciprocal channel supports signal transport in two directions with the same transmission properties. Nonreciprocal devices do not obey this general symmetry, and therefore enable isolation and circulation, offering fundamental functionalities in modern GHz-to-THz photonic systems. While most nonreciprocal devices to date are based on magneto-optical phenomena, significant interest has been raised by approaches that avoid the use of magnetic materials, instead relying on artificial materials and circuits that mimic magnetically biased ferrites, enabling compact, light, integrated, and significantly cheaper nonreciprocal devices. Here, we review recent progress in and opportunities offered by artificial nonmagnetic materials that break reciprocity, revealing their potential for compact nonreciprocal devices and systems.

Ferroelectrics are promising for nonvolatile memories. However, the difficulty of fabricating ferroelectric layers and integrating them into complementary metal oxide semiconductor (CMOS) devices has hindered rapid scaling. Hafnium oxide is a standard material available in CMOS processes. Ferroelectricity in Si-doped hafnia was first reported in 2011, and this has revived interest in using ferroelectric memories for various applications. Ferroelectric hafnia with matured atomic layer deposition techniques is compatible with three-dimensional capacitors and can solve the scaling limitations in 1-transistor-1-capacitor (1T-1C) ferroelectric random-access memories (FeRAMs). For ferroelectric field-effect-transistors (FeFETs), the low permittivity and high coercive field Ec of hafnia ferroelectrics are beneficial. The much higher Ec of ferroelectric hafnia, however, makes high endurance a challenge. This article summarizes the current status of ferroelectricity in hafnia and explains how major issues of 1T-1C FeRAMs and FeFETs can be solved using this material system.

Material development has played a crucial role in modern civilization and IT. The importance of high-density and high-performance memory in modern computer systems and IT is ever increasing. This trend will be more obvious as computational architectures shift from being processing-centric to memory- (or data-) centric. The need for emerging and new memory technologies with nonvolatility and low power-consuming performance is rapidly increasing, while improvements in current dynamic random-access memory and NAND flash are being pursued. In both new and current memories, material innovation is of central importance. In this issue of MRS Bulletin, recent improvements in these two critical fields are reviewed with a focus on emerging and novel materials for the disruptive memory concept. Recent progress in scanning probe-based memory devices is also described.

The ability to interface electronic materials with the peripheral nervous system is required for stimulation and monitoring of neural signals. Thus, the design and engineering of robust neural interfaces that maintain material-tissue contact in the presence of material or tissue micromotion offer the potential to conduct novel measurements and develop future therapies that require chronic interface with the peripheral nervous system. However, such remains an open challenge given the constraints of existing materials sets and manufacturing approaches for design and fabrication of neural interfaces. Here, we investigated the potential to leverage a rapid prototyping approach for the design and fabrication of nerve cuffs that contain supporting features to mechanically stabilize the interaction between cuff electrodes and peripheral nerve. A hybrid 3D printing and robotic-embedding (i.e., pick-and-place) system was used to design and fabricate silicone nerve cuffs (800 µm diameter) containing conforming platinum (Pt) electrodes. We demonstrate that the electrical impedance of the cuff electrodes can be reduced by deposition of the conducting polymer poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) on cuff electrodes via a post-processing electropolymerization technique. The computer-aided design and manufacturing approach was also used to design and integrate supporting features to the cuff that mechanically stabilize the interface between the cuff electrodes and the peripheral nerve. Both ‘self-locking’ and suture-assisted locking mechanisms are demonstrated based on the principle of making geometric alterations to the cuff opening via 3D printing. Ultimately, this work shows 3D printing offers considerable opportunity to integrate supporting features, and potentially even novel electronic materials, into nerve cuffs that can support the design and engineering of next generation neural interfaces.

Chip-package interaction (CPI) and the related thermomechanical stress in microchips increase the risk of failure in on-chip interconnect stacks, caused by delamination along Cu/dielectrics interfaces (adhesive failure) and fracture in dielectrics (cohesive failure). High-resolution transmission X-ray microscopy (TXM) is a unique technique to image crack propagation in on-chip interconnect stacks. The visualization of crack evolution in Cu/low-k Backend-of-Line (BEoL) structures is demonstrated using an experimental setup which combines high-resolution X-ray imaging with mechanical loading. The application of an indenter manipulator at the TXM beamline of the synchrotron radiation source BESSY II provides an unprecedented level of details on the fracture behavior of microchips. This in-situ experiment allows to identify the weakest layers and interfaces and to evaluate the robustness of the BEoL stack against CPI.

In this study, we present a 4-channel intracortical glassy carbon (GC) microelectrode array on a flexible substrate for the simultaneous in vivo neural activity recording and dopamine (DA) concentration measurement at four different brain locations (220µm vertical spacing). The ability of GC microelectrodes to detect DA was firstly assessed in vitro in phosphate-buffered saline solution and then validated in vivo measuring spontaneous DA concentration in the Striatum of European Starling songbird through fast scan cyclic voltammetry(FSCV). The capability of GC microelectrode arrays and commercial penetrating metal microelectrode arrays to record neural activity from the Caudomedial Neostriatum of European starling songbird was compared. Preliminary results demonstrated the ability of GC microelectrodes in detecting neurotransmitters release and recording neural activity in vivo. GC microelectrodes array may, therefore, offer a new opportunity to understand the intimate relations linking electrophysiological parameters with neurotransmitters release.