A robust copper slurry should have high removal rate, efficient planarization, optimal over polishing window and fast clearing without corrosion. These requirements were addressed in the choice of abrasive particles, film formation for copper passivation, selectivity of copper to barrier, and interactions between particles and film surfaces. The performance results of low dishing erosion and surface finish are discussed with the proposed mechanism.

The use of cerium oxide (ceria) as an abrasive for dielectric chemical mechanical polishing has a “checkered” history to say the least. Nevertheless, its use remains attractive for this purpose because of favorable polishing characteristics that are generally not obtainable using conventional fumed or colloidal silica abrasives. To be specific, large differences are commonly observed between removal rates of thin film silicon oxide, silicon nitride, and/or polysilicon. Moreover, such rate selectivity invariably favors removal of oxide films, which of course, is precisely what is desirable for fabrication of modern shallow trench isolation schemes. Even so, CMP using ceria abrasive often exhibits unusual characteristics that cannot be explained adequately by conventional polishing models based on pad/asperity elasticity or pressure distribution over features. Most notably, non-conventional, observed behaviors can be collected under the rubric of “slow start phenomena”. In this work, it is asserted that specific polishing characteristics of ceria slurry are largely due to the detailed surface chemistry of ceria particles and their interaction with silica. In any case, it is further shown that modification of slurry lubrication can alleviate slow-start and shift CMP process characteristics back toward more conventional behavior.

Duel Emission Laser Induced Fluorescence (DELIF) and friction measurements are taken in-situ during CMP to observe slurry flow beneath a model of an integrated circuit (IC) wafer. Friction measurements average around 7.5 lb and multiple frequencies are observed. Slurry film thicknesses on the order of a 10±3μm were observed during CMP of a flat wafer. The film thickness seems uncorrelated to friction measurements except when the pad and wafer rotation speeds are significantly slowed. DELIF has also accurately measured a 9μm etched step, with noise in the image equal to ±3 μm.

The current bedrock technology for integrated circuit (IC) planarization, chemical-mechanical polishing is beginning to play an important role in microelectromechnical systems (MEMS). However, MEMS devices operate with bigger feature sizes in comparison to ICs, in order to fulfill mechanical functions. We present an experiment to characterize and model a polysilicon CMP process with the specific goal of examining MEMS-sized test structures. We utilize previously discussed CMP models and examine whether assumptions from IC CMP can be applied to MEMS CMP. An analysis of the data collected points to a polishing dependence on not only pattern density, but also partly on feature size or feature configuration. The existing pattern density and step height CMP models are able to capture the major trends in up and down area polishing. However, certain layout features relevant to MEMS are difficult to predict, motivating the need for further model development and application.

The new approach using Fixed Abrasive (FA) pads for polishing thick film Silicon-on- Insulator (SOI) wafers after bonding and grinding process [1] has been further developed. The aim is a practicable industrial manufacturing process, where the major specifications especially in long term stability and removal rate should be achieved. In base line studies a stable removal rate on suitable level has been reached, while the degeneration of the total thickness variation (TTV) was limited to a clearly smaller value than that being typical for the standard stock removal polishing. The overall removal in these tests was adjusted to 2-3 μm, which removes all sub surface damage (SSD) from wafers ground by ultra fine grinding wheels with very small average abrasive particle size. The process has been able to remove all visible grindlines after removing less than 1.5 μm. In another test with a further developed high density FA pad, removal rates up to ∼0.6 μm/min were achieved. The polished samples were further processed and characterized by capacitive thickness measurements gauges, optical surface inspection tool (“Magic mirror”), atomic force microscopy (AFM) and optical reflection measurements.

To achieve 65 nm technology node requirements, CMP processes must provide improved control of selectivity, topography, wire cross section, and process robustness. Slurries and processes must also be compatible with fragile low k materials by providing low erosion and shear forces. We present data on a unique step 1 bulk Cu removal slurry with high selectivity, removal rates over 8000 Å/min, and extremely low liner removal/erosion in high (90%) density structures. This is achieved through a combination of surface modified abrasives and alternative inhibitors which provide superior performance and reduced electrochemical activity compared to benzotriazole, a commonly used inhibitor. The step 1 slurry was used with a step 2 liner removal slurry that can be chemically tuned to adjust relative selectivities of Cu:Ta:oxide from the nominal ratio of 1:0.9:1.6, allowing its use with a variety of integration schemes. Results of CMP planarization experiments on 200 mm blanket and patterned single damascene test wafers are described, including electrical data which demonstrates low overpolish sensitivity.

A 3-D fluid flow and kinetics model of the full pad-wafer gap of a commercial CMP machine, including both grooves and land area flow properties, was developed to research the influence of these essential pad features at a scale not previously studied. Concentric circular grooves of two different dimensions were examined. Heat transfer and chemical reaction rates at the wafer surface were studied by including a combined frictional/chemical heat release model and firstorder kinetics for slurry activity. Results revealed sharp variations in velocity between the grooves and land areas, and a strong impact of groove depth and width on transient slurry mixing in the pad-wafer gap. These effects were more pronounced at higher polish pressures. Flow patterns in individual grooves beneath the rotating wafer were highly variable from one location to another such that fluid pathlines were dissimilar point to point even within the same groove. The effects of pad and wafer rotation, amplified by the unequal flow resistances of grooves and land areas, led to features in the steady-state temperature and concentration profiles at the same spacing as the groove pitch. This unusual finding identified a direct mechanism by which polish irregularities may be formed at the scale of the grooves.

Chemical mechanical polishing (CMP) has become the enabling planarization method for shallow trench isolation (STI) of sub 0.25μm technology. CMP is able to reduce topography over longer lateral distances than earlier techniques; however, CMP still suffers from pattern dependencies that result in large variation in the post-polish profile across a chip. In the STI process, insufficient polish will leave residue nitride and cause device failure, while excess dishing and erosion degrade device performance.

Our group has proposed several chip-scale CMP pattern density models [1], and a methodology using designed dielectric CMP test mask to characterize CMP processes [2]. The methodology has proven helpful in understanding STI CMP; however, it has several limitations as the existing test mask primarily consists of arrays of lines and spaces of large feature size varying from 10 to 100 μm. In this paper, we present a new STI characterization mask, which consists of various rectangular, L-shape, and X-shape structures of feature sizes down to submicron. The mask is designed to study advanced STI CMP processes better, as it is more representative of real STI structures. The small feature size amplifies the effects of edge acceleration and oxide deposition bias, and thus enables us to study their impact better. Experimental data from an STI CMP process is shown to verify the methodology, and these secondary effects are explored. The new mask and data guide ongoing development of improved pattern dependent STI CMP models.

Surface texture of CMP polishing pads varies considerably with the intrinsic microstructure of the pad, the addition of perforations or grooves, and the means of surface conditioning. The state of pad-wafer contact is determined by both large and small-scale texture in the top pad asperity layer and by the interaction of the top pad and sub-pad.

A flow-based texture characterization test was applied to several types of CMP polishing pads to describe the asperity layer as a porous media having a void fraction and characteristic length. Fluid pressure loss profiles were measured in a radial flow geometry across pad samples pressed against a flat instrumented plate. Symmetry of the profiles revealed the extent of contact between the pad and the plate, and curvature of the profiles showed the relative contributions of viscous and inertial flow among the asperities. Sub-pads, grooving, and conditioning all increased padwafer contact and the effective resistance of the surface texture, improving flow uniformity. Soft pads showed higher inertial flow influence than fixed abrasives with regularly spaced asperities. The results demonstrate that pad surface texture has a strong influence on heat and mass transfer at the wafer surface in CMP. Implications are discussed for both pad design and CMP modeling.

Due to the ever-increasing popularity of STI in microelectronic device fabrication, designer slurries must be tailored to meet increasingly stringent planarity requirements. Although dielectric polishing is primarily mechanical in nature, the chemical and surface chemical effects can be tailored to enhance selectivity and planarity. Examples of chemical and surface chemical effects in dielectric CMP include; control of slurry pH, use of reactive particles such as cerium dioxide, and addition of surfactants to modulate the particle-substrate interactions. Cerium dioxide particles are utilized due to an increase in substrate dissolution through particle-substrate bonding, which accelerates the material removal of the dielectric surface. The increased efficiency of reactive particles is largely dependent on the area of contact between particle and substrate during polishing. The chemical nature of the interaction between the particles and silica substrates has been investigated using polishing experiments, AFM, and an in-situ friction force apparatus. Both the pH and cerium dioxide particles have been found to significantly affect the near surface region of the oxide film.

Chemical Mechanical Planarization has become a method of choice for planarization of metal and oxide layers in microelectronics industry. A CMP process includes up to 16 variables that need to be controlled to achieve a stable CMP process [1]. One of the major variables in CMP is related to slurry compositions. In particularly, a uniform distribution of the sizes of the abrasive particle in slurry is crucial for a stable CMP performance. The agglomerates can be unstable, since their size depends on addition of chemical additives and shearing during the CMP process.

In this work, the authors studied agglomeration of the fumed and colloidal silica-based slurries using dynamic rheometry, zeta potential tests, and an accusizer.

Slurry viscosity, determined using a steady state rheometry, was correlated to the particle charge, characterized by zeta potential, and to the particle sizes obtained using the particle size analyzer. Additionally, rheometer was used for slurry shearing to study effect of shear on slurry characteristics. Particle agglomeration due to slurry shearing and storage was observed and corroborated using rheometry, zeta potential, and particle size measurements.

There is a need to develop a metrology metrics for evaluation of pad CMP performance before putting them in to service. This has been attempted on Psiloquest's application specific pads (ASP) in which the pad surface is tuned to match the mechanical properties of the target substrate. The ASP is made up of thermoplastic foams co extruded with condensed polyolefin. The chemical and mechanical properties of the pad-wafer interface are tuned by coating the pad with ceramic thin films by surface coating method such as chemical vapor deposition (CVD). The surface of the pad is characterized using metrology techniques such as ultra sound reflectivity, XPS and nanoindentation. The cross section of the pads was characterized using SEM. The mechanical properties of bulk pad materials were studied using Dynamic Mechanical Analysis (DMA). A test was performed on the pads to measure the static coefficient of friction (COF) and wear rate. The pads were polished using CETR CP-4 bench top CMP tester to evaluate the dynamic COF, Acoustic Emission (AE) signal and removal rate during a simulated Tungsten CMP process. The thickness of the ceramic coating on the surface of the ASP played an important role in determining these tribological properties. The results of the various static and dynamic tests performed on the pad were cross tabulated to evaluate their correlation.

Local material removal rate is inversely proportional to the local pattern density in ILD CMP. With the assumption that the local velocity and Preston coefficient are constant across a chip, local MRR non-uniformity is mainly attributed to the local pressure non-uniformity. Pressure distributions on two different test patterns consisting of five different pattern density sections were obtained with a finite element model. These pressure distributions were compared with output from a semi-empirical pattern dependent oxide CMP model (MIT model) with three different weighting functions. Result showed that pressure distribution could be well approximated with the pattern density dependent oxide CMP model. This FEM model was further taken to evaluate the effects of thickness and material properties of each layer on the degree of pattern dependant pressure non-uniformity at a die scale for a typical polishing pad made up of a hard and a soft layer. The analysis shows that the degree of pressure nonuniformity at a die scale increases with the combination of a stiff hard layer and a thick soft layer, while it decreases with the combination of a stiff soft layer and a thick hard layer.

New abrasive particles based on SiO2 and Al2O3 were produced with different coating and doping. Seven specifically designed particles were dispersed to prepare slurries for Cu CMP. Glycin was used as complexing agent and hydrogenperoxid as oxidizer. The experimentally obtained removal rate, selectivity, surface quality and planarisation ability, demonstrate a significant impact of the different abrasives tested. SiO2 particles covered with Al2O3 increased the removal rate for Cu. In comparison to this behavior, a low rate for TaN proved a high selectivity copper removal required by the Cu CMP process. A new method for the planarisation length monitoring (step polish response) shows also significant differences in planarisation length (PL) by the polish of copper with slurries composed of these new particles.

CMP(Chemical Mechanical Planarization) process is widely used to reduce step height in semiconductor fabrication processes. As a design rule shrinks, a highly planar surface becomes inevitable within wafer scales. In order to get a high degree of a planarization, self-stopping characteristics of a ceria-based slurry should be studied and used in semiconductor process. In this study, threshold polishing pressure for a self-stopping characteristics was obtained by optimizing down pressure, pad conditioning, and mixing ratio of ceria abrasive and additive. A series of experiments were made to optimize the threshold polishing pressure in variable line & space patterns that consist of 0.8um step height and unit oxide film. As a result, self-stopping cmp process is twice batter than conventional silica-based process with respect to planarity and WIWNU. In addition, WIWNU and step height was dramatically decreased to less than 1000Å when applying to real fabrication devices over 2um step height.

In this research, we present an improved and coherent chip-scale model framework for copper bulk polishing, copper over-polishing, and barrier layer polishing. The integration of contact wear and density-step-height models is more seamlessly implemented and addresses inherent shortcomings of the previous model. In the new model, a local density is used instead of the effective density computed by way of a planarization length, and only a contact wear coefficient is used to characterize the long-range planarization capability, thus avoiding the conflict between the planarization length and the contact wear coefficient in capturing topography variation. In addition, the pressure computed for each 240×240 μm block using contact wear is further redistributed, using a linear height vs. pressure model, among 40×40 μm cells within that block. The same model framework is used for different polishing steps, so that it is possible to directly compare basic process characteristics, such as pad stiffness, of different polishing stages. Results with the new model show a significant improvement of the modeling accuracy to less than 100 Å of root mean square error. Furthermore, the new model framework can be adapted for the modeling of multi-level metallization processes.

Monolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.