This chapter introduces the fractional-N synthesizer, which is also aimed at GSM applications with a supply voltage of 1.5 V. The synthesizer employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, a low-supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5 μm CMOS process, a fully integrated fractional synthesizer prototype with a third-order sigma–delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is around 1.0 mm2. The settling time is less than 250 μs, and the phase noise is better than −115 dBC/Hz at 600 kH3 offset.

Introduction

In monolithic phase-locked-loop (PLL) frequency synthesizer design, the phase noise performance of the synthesizer is degraded not only by the phase noise of the voltage-controlled oscillator (VCO) itself and the noise from the loop filter, but also by the substrate noise. Since the substrate is conductive, any noise generated from other circuits will couple through the substrate to the VCO and degrade the phase noise. This noise source is difficult to predict and cannot be prevented or reduced significantly even by increasing power consumption. Large separation from noise sources and guard rings can help reduce substrate coupling, but the effectiveness is quite limited in practice due to the compact layout for a small chip area.

Switching speed is limited in PLL-based synthesizers.