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8 - A 1 V 5.2 GHz fully integrated CMOS synthesizer for WLAN IEEE 802.11a

Published online by Cambridge University Press:  22 October 2009

Howard Cam Luong
Affiliation:
Hong Kong University of Science and Technology
Gerry Chi Tak Leung
Affiliation:
Hong Kong University of Science and Technology
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Summary

A very low voltage synthesizer designed for WLAN is introduced in this chapter. Novel circuit designs discussed in Chapter 5 are demonstrated, such as for the VCO and programmable divider. The measured phase noise is −136 dBc/Hz at an offset of 20 MHz from the carrier, while the spurious tone is better than −80 dBc at the offset of the reference clock frequency. The synthesizer dissipates 27.5 mW from a single 1 V supply. The total core area occupies 1.03 mm2.

WLAN overview

IEEE 802.11a is a new standard aimed at high-speed wireless LAN communication systems. A high data rate of up to 54 Mbps can be offered between portable devices. It is designed for the 5 GHz frequency spectrum employing orthogonal frequency division multiplexing (OFDM) as its modulation scheme.

IEEE 802.11a is allocated a bandwidth of 300 MHz, which is separated into three bands with 100 MHz for each, according to different transmitting powers (Fig. 8.1). The three bands are the lower band, the middle band and the upper band. The lower band and middle band are specified for indoor communication, and the maximum transmit powers are 40 mW and 200 mW, respectively. The upper band is suited for outdoor use with a larger transmitting power of up to 800 mW. Each band contains four channels and each channel occupies 20 MHz bandwidth with 48 data sub-carriers, four pilot sub-carriers, and one nulled sub-carrier. Another 11 sub-carriers are discarded during signal processing (Agilent, 2003).

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Publisher: Cambridge University Press
Print publication year: 2004

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