Introduction

The impact of low-voltage design is degradation in speed, because of limited driving capability, and in signal-to-noise ratio (SNR), because of the reduced signal swing. In addition, for synthesizer designs, a low supply voltage reduces the frequency tuning range and degrades the phase noise unless the current and power consumption are increased. Moreover, the design of prescalers and high-speed digital circuits becomes much more challenging because of the speed degradation of digital circuits with a low-voltage supply. This chapter discusses these design considerations and presents some of the design techniques required for critical building blocks in RF CMOS synthesizers as the supply voltage is lowered.

System considerations

The control voltage of the VCO in a synthesizer becomes limited under a low supply voltage. This results in a limited frequency tuning range with a given VCO gain. A larger VCO gain could be used to compensate for the degradation of the tuning range at the expense of the phase-noise and spurious-tone performance of the system. A high loop bandwidth helps to improve rejection of the VCO phase noise but sacrifices the spurious-tone suppression. In contrast, a small PLL loop bandwidth can provide larger spurious-tone suppression but results in less rejection of the VCO phase noise. On other hand, LC oscillators can achieve better phase noise than ring oscillators for a given power. As a consequence, a synthesizer using an LC oscillator with a small loop bandwidth can attain optimized performance in terms of noise and spurious suppression.