Spin-on pure-silica-zeolite MFI films consist of zeolite nanocrystals embedded in a compacted silica matrix of zeolite primary nanoparticles. They appear to be promising as a low-k material due to their good mechanical properties and high microporosity, parallel to their intrinsic low k-value. Results are promising but the implementation of this material is still far away. To contribute to the implementation we present a study on the final film properties depending on the zeolite MFI nanocrystal size. Different techniques are used for the characterization: Dynamic Light Scattering, X-ray diffraction, Scanning Electron Microscopy, Nitrogen adsorption, EllipsoPorosimetry using toluene and NanoIndentation. The results show a clear dependence of the film properties on the nanocrystal size. Clearly, smaller nanocrystals provide better homogeneity, smaller pore size and higher mechanical properties. However, due to the hydrophilicity of the silica matrix lower k-values are only obtained for larger zeolite nanocrystals which provide with higher crystallinity in the films.

We present the influence of the electrochemical plating recipe and the bath chemistry on Cu grain size evolution and its link to corrosion of Cu interconnects. Our results demonstrate the fact that Cu corrosion depends on the combination of (i) solution type and (ii) Cu quality. The latter is influenced by geometrical factors such as line width and pattern density as well as the electroplating parameters such as plating recipe and bath chemistry. Organic and inorganic acid based model-CMP solutions are used to make a comparison in terms of the interactions with the Cu surface. It is shown that an organic acid based solution etches Cu independent of the Cu quality. However, etching by an inorganic acid based solution reveals line width (0.2 μm <w<1.0 μm) and pattern density dependence (16%< pd< 72 %) with the narrow lines being etched more rapidly both for isolated and semi-dense structures. This kind of geometry dependent etch behavior by the inorganic acid based solution is also shown to be a function of the electroplating process parameters in contrast to an organic acid based one.

In advanced CMOS technology nodes one may achieve further enhancement of device performance by carrier mobility modification in the transistor channel. The carrier mobility enhancement can be realized by formation of strained silicon layers on a Si1−xGex strain relaxed buffer. Formation of source and drain extensions on such structures need to satisfy one additional requirement, the formation process, including the activation related thermal budget should not relax the strain in the channel. In this paper we separately investigate the role of amorphization during implantation, different doping impurities and thermal budget on the junction and the transistor channel regions properties. Two approaches of dopant activation are discussed: low temperature solid phase epitaxial regrowth and high temperature conventional spike.

The damage induced in the low-k material upon exposure to dry etch and ash plasmas is a point of major concern in terms of preservation of the dielectric properties. There is urgent need to assess, classify and quantify the extent of such damage to allow the optimization of patterning processes and conditions. Meander-fork structures with spacings between 250nm and 70nm are used in this study as vehicle to compare trends in electrical performance for different dielectrics: SiO2 and two SiOC:H low-k materials with pristine k values of 3.0 and 2.6. Here we demonstrate that the ‘electrical equivalent damage’ model is a valid and precise methodology for assessing dielectric damage upon processing from interline capacitance evaluation. This analysis allows to distinguish between bulk and sidewall modification and to quantify the extent of damage. Moreover, it provides an interpretation for the degradation of leakage current and breakdown field of the interline dielectric, revealing different trends whether due to only sidewall or total damage.

Cross-section nano-indentation is a technique that consists of cleaving a wafer, indenting behind the stack on the side surface causing delamination, and measuring the delaminated area in an optical microscope. It is shown to be a reliable rapid technique for adhesion evaluation and process optimization of the SiO2/barrier/copper stack.

The creation of ultra-shallow junction for CMOS devices at the sub-100 nm node is driving significant efforts in developing thermal processing to give rise to high dopant activation in combination with limited diffusion. Flash-assist Rapid Thermal Annealing™ (fRTP™) is a promising new annealing technique, which involves the heating of the bulk of the wafer to an intermediate temperature using rather conventional spike RTP, followed by a short and intense pulse of light localized on the implanted wafer surface.

In this work, we have systematically investigated the junction formation of different implants under fRTP anneals in terms of profile and devices. Co-implanted Ge and F species provide more box-like profiles with improved activation. Although leakage currents are higher for fRTP-annealed junctions than for spike-annealed junctions, appropriate fRTP process parameters and correct process conditions provide a critical tool to control and reduce the leakage current of co-implanted fRTP junctions to acceptable levels. Proper implant and anneal are requested for minimizing pattern effect and improving device performance.

Nucleation can play an important role during the formation of silicides, especially when the difference in Gibbs free energy ΔG between the existing and newly formed phase is small. In this work, it is shown that the addition of elements that form a solid solution with either the existing or nucleating phase influences the entropy of mixing and thus changes ΔG. In this way, the height of the nucleation barrier may be controlled, thus controlling the nucleation temperature. The influence of mixing entropy on silicide nucleation is illustrated by experiments for two ternary systems: Co–Mn–Si and Ni–Pd–Si. It is shown that the nucleation temperature of CoSi2 is increased by the addition of Mn, the nucleation temperature of MnSi1.7 is increased by the presence of Co, the nucleation temperature of NiSi2 is increased by the addition of Pd, and the nucleation temperature of PdSi is decreased by the addition of Ni. In all four cases, the effect of the alloying element on the nucleation temperature can be explained by a model on the basis of the concept of mixing entropy.

We investigated the corrosion mechanism of copper films. Based on our results regarding the morphology of the Cu surface, examined by scanning electron microscopy (SEM) and focused ion beam (FIB), it is shown that with an inorganic acid-based model CMP solution corrosion is initiated at the grain boundaries. In contrast, for an organic acid-based solution, corrosion starts with no preferential location. Some of the samples received an additional anneal after the CMP process was completed to monitor the influence of annealing on the corrosion mechanism by the acid solutions. Presence of facets especially after treatment with the inorganic acid-based model CMP solution suggests that a different mechanism governs the initiation and the evolution of corrosion. Desorption of the impurities during annealing, which is monitored by Atmospheric Pressure Ionized Mass Spectrometry (APIMS) revealed desorbing species from the copper films that could originate from the additives used in the Cu plating bath.

Low-k dielectrics are currently starting to replace SiO2 in advanced on-chip interconnects. Being low surface energy materials, a major concern for the integration of such dielectrics in Cu damascene processes is given by adhesion failure at the interfaces of the low-k films with cap or liner layers during Chemical Mechanical Polishing (CMP). A cross-comparison between interface fracture energies as measured through four-point bending, CMP experiments and stress fields computed by Finite Element Modeling, shows that it is not possible to predict failures by setting a ‘universal’ threshold on adhesion strength.

In particular, we report on the critical role of CMP –induced shear stress on the onset of interface debonding, and the way the shear load is transmitted to the critical interfaces. The top-down load transmission depends on the position of the weak interfaces, and on the way the intermediate films in the stack can confine such load through their thickness and mechanical (elastic and plastic) properties.

Due to integration concerns, the use of meta-stable junction formation approaches like laser thermal annealing (LTA), solid phase epitaxial regrowth (SPER), and flash annealing has largely been avoided for the 90nm CMOS node. Instead fast-ramp spike annealing has been optimised along with co-implantation to satisfy the device requirements, often with the help from thin offset spacers. However for the 65nm and 45nm CMOS node it is widely accepted that this conventional approach will not provide the required pMOS junctions, even with changes in the transistor architecture.

In this work, we will compare junction performance and integratablity of fast-ramp spike, flash, SPER and laser annealing down to 45nm CMOS. The junction depth, abruptness and resistance offered by each approach are balanced against device uniformity, deactivation and leakage. Results show that the main contenders for the 45nm CMOS are SPER and flash annealing – but both have to be rigorously optimised for regrowth rates, amorphous positioning and dopant and co-implant profiles. From the two, SPER offers the best junction abruptness (<1nm/dec) with leakage suitable for low power applications, while the flash anneal has the benefit of higher solid solubility (>4E20at/cm3) and less transistor modifications. As expected, Ge and F co-implanted spike annealed junctions do not reach the 45nm node requirements. For full-melt LTA, poly deformation on isolation can be reduced but geometry effects result in unacceptable junction non-uniformity.

The widely observed secondary grain growth in electroplated Copper layers is shown to be incomplete after the sheet resistance and stress of the layer appear to have stabilized. Instead the layer is in an intermediate state with a grain size distribution that depends on the plating conditions. Further extensive annealing at high temperatures results in an additional considerable enlargement of the grain structure, accompanied by an additional decrease of the sheet resistance and desorption of impurities that were incorporated during plating.

Compressive stresses in thin capping films deposited onto low-k dielectric substrates are particularly prone to relaxation through buckling. This is due to insufficient cap/low-k film adhesion energy and to the compliance of low dielectric constant films. Low-k dielectric films, especially when porous, have low elastic modulus and demonstrate poor adhesion to other layers.

When adhesion is poor the cap film can locally buckle as if unconstrained. The buckle front can propagate like a crack and lead to complete delamination of the cap layer. If the cap/low-k film adhesive energy is high, wrinkling instabilities can take place under specific conditions determined by the geometry and the mechanical properties of the stack. In this case the dielectric also deforms due to stress relaxation. A theoretical and experimental evaluation of the parameters influencing the occurrence of these instabilities is presented. This study was carried out to explore the application and reliability of low-k materials as dielectrics for advanced interconnects.

The results of an in situ transmission electron microscopy study of the formation of Co-silicides on patterned (001) Si substrates are discussed. It is shown that the results of the in situ heating experiments agreed very well with the data based on standard rapid thermal annealing experiments. Fast heating rates resulted in better definition of the silicide lines. Also, better lines were obtained for samples that received already a low-temperature ex situ anneal. A Ti cap layer gave rise to a higher degree of epitaxy in the CoSi2 silicide.

A reactive Ti capping layer is needed to getter oxygen contamination and to make the cobalt silicidation reaction a more robust process. However, the presence of a Ti capping layer induces two other effects (in addition to the beneficial gettering of oxygen impurities): the formation temperature of CoSi2 is increased and the CoSi2 layer has a strong (220) preferential orientation. Because of the current technological importance of the Ti/Co/Si system, we have made a detailed investigation of the influence of several process parameters (annealing temperature, selective etching, layer thickness) on the nucleation of CoSi2 in the Ti/Co/Si system. Moreover, it is shown that the addition of Ni (i.e. a Ti/Co/Ni/Si or Ti/Ni/Co/Si structure) causes a decrease of the CoSi2 nucleation temperature.

In this work we present investigations of the nucleation and growth of evaporated copper on several low-k polymers. The evolving interfaces were characterized using transmission electron microscopy (TEM), x-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). The results were compared between the PMDA/ODA polyimide, Teflon AF 1601 and Silk®. A diffusion coefficient for copper atoms in Silk® determined by low energy ion-beam depth profiling in conjunction with XPS is reported.

In this work, AFM and sheet resistance measurements are used to characterize the thermal stability of thin CoSi2 films. We were particularly interested in the influence of different multilayer structures on the topography and surface roughness. Four different multilayer structures (Co/Si, TiN/Co/Si, Ti/Co/Si and Co/Ti/Si) were investigated. Thermal degradation of CoSi2 formed from a standard Co/Si structure is found to have an activation energy of about 4.2 eV, independent of layer thickness (in agreement with previous results by Alberti et al.). A TiN capping layer is shown to improve the thermal stability. However, if the TiN layer is too thick (e.g. 50 nm), a new failure mode is observed: although the TiN prevents grain boundary grooving of the silicide, the thermal stress induced by the TiN causes the CoSi2 layer to crack. For a Ti capping layer, a strong increase of the thermal stability of the CoSi2 layer is observed, even if the Ti capping layer is removed by a selective etching step after the first RTP annealing. The presence of a very thin Ti-O-N containing layer on the CoSi2surface seems to strongly decrease surface diffusion and in this way reduce the tendency for grain boundary grooving.

Evidence is presented that the nucleation of CoSi2 can be influenced by the presence of small amounts of other elements. The presence of trace amounts of Ti in the CoSi (originating from either a Ti capping layer or interlayer) causes an increase in the CoSi2 nucleation temperature. Moreover, the presence of Ti in the CoSi induces a preferential orientation of the CoSi2 : for an increasing amount of Ti, we observed a transition from polycrystalline CoSi2 over preferential (220) orientation towards epitaxial (400) CoSi2. We observed similar effects for other elements (e.g. Ta, W, C, Mo, Cr). We were able to explain these findings based on the heterogeneous nucleation of CoSi2.

It is generally known that nucleation effects strongly influence the CoSi to CoSi2 phase transition. According to classical nucleation theory, the small difference in Gibbs free energy between the CoSi and CoSi2 phase is responsible for the nucleation barrier. Adding elements that are soluble in CoSi and insoluble in CoSi2 will influence the entropy of mixing, and thus change ΔG. In this way, the height of the nucleation barrier may be controlled.

By depositing Fe or Ge (respectively replacing Co and Si in the CoSi lattice) in between the Co and the Si substrate, we were able to increase the nucleation barrier. In the presence of Ni, the nucleation barrier is lowered, and low-resistive disilicide is formed at lower temperatures.

The adhesion between several materials implemented in Cu/low-k integration is studied. Adhesion issues at different interfaces are important with regard to the reliability of back-end processing. Layered test structures are processed to study different interfaces. A tangential shear tester allows quantifying the adhesion force at the interface and provides a relative measurement to compare various materials. Failed interfaces are analyzed using auger electron spectroscopy (AES) and scanning electron microscopy (SEM). Among all studied structures, the strongest interface is seen between a barrier (Ti(N), Ta(N), WxN) and Cu. A weaker interface proves to be between a low-k dielectric and Cu. However, the presence of a barrier increases the adhesion. The weakest interface occurs between an oxide cap and the low-k material, with a lower adhesion when the low-k material is fluorinated. The low-k/cap oxide interface forms a critical issue with regard to Cu/low-k integration processing such as chemical mechanical polishing (CMP). All test structures show no significant degradation of the adhesion after a thermal cycle up to 400°C.

We have studied CoSi2 formation in the presence of a Cr or Mo interlayer or capping layer. We shall show that, contrary to what was previously reported, Cr and Mo may be used as interlayers to grow epitaxial CoSi2. However, unlike for Ti, the thickness of the interlayer is very important. If the Cr or Mo interlayer is too thick (> 5 nm), polycrystalline CrSi2 or MoSi2 are formed first and epitaxial growth of CoSi2 becomes impossible. However, both XRD and random/channeling RBS results indicate that for a 2-3 nm interlayer of Cr or Mo, CoSi2 forms epitaxially on Si(100). For thinner interlayers, there is a preferential (220) and (400) orientation. This can be explained by the presence of Cr or Mo on the CoSi grain boundaries, which will affect the heterogeneous nucleation of CoSi2.