A nanopatternable oligomeric PDMS layer has been first verified as a nano-adhesive for its intrinsic transferability and universal adhesiveness. Utilizing the well-established PDMS surface modification and bonding techniques, we have been able to form irreversible bonding between a wide range of substrate pairs, representing ones within and across different material categories, including metals, ceramics, thermoset, and thermoplastic polymers. The anisotropic conductivity of the PDMS oligomer nano-adhesive has been investigated, which allows specific and excellent directional conductivity between bonded electrodes without risk of electrical shorts across different contacts.

Flexible devices utilizing crystalline semiconductor nano or microstructures materials are attractive for many applications. However, these materials are fabricated or grown in unusable forms for flexible systems due to their rigid crystalline mother substrates. We demonstrate a transfer printing technique for transferring vertical arrays of one-dimensional (1D) materials from mother substrates to flexible substrates with subsequent device fabrication steps to create flexible devices from these arrays. The transfer printing technique is based on vertical embossing of arrays of 1D materials into thermoplastic (Poly (methyl methacrylate) (PMMA)) transfer layers, while the device fabrication steps rely on encapsulation with insulating polymers and contact deposition. We investigated the use of flexible insulating layers like polydimethylsiloxane (PDMS) and polyurethane (PU) which are shown to be effective for encapsulation and contact isolation. Representative flexible resistive devices were created from these transferred arrays and insulating layers which showed a reversible tactile characteristic. Electronic characterization and flexibility testing was carried out to show the potential of these methods for enabling large-scale integrations of nano and microstructures into vertical and flexible packages.

The theoretically-predicted enhancement of metal-graphene contacts using the “end-contacted” configuration is studied. Graphene edges at the source/drain regions are created via a CMOS process compatible metal-assisted etching technique. The on-resistance of a graphene device with cobalt-etched-graphene contacts shows 6 times improvement compared to pristine graphene device. Apart from that, four-point contacted graphene devices with nickel-etched-graphene contacts were fabricated and tested under ambient conditions. The proposed graphene devices exhibit contact resistance as low as 14 Ωμm, with an average of 90 Ωμm. Thus, forming metal-etched-graphene contacts is a promising method to obtain low-contact resistance metal contacts to graphene.

As ohmic contacts decrease in size and approach nanoscale dimensions, accurate electrical characterization is essential, requiring the development of suitable test structures for this task. We present here a new test structure derived from the standard three-contact circular transmission line model (CTLM) [1], for determining the specific contact resistivity of ohmic contacts. This test structure minimizes sources of error which arise from the CTLM by – (i) reducing the number of contacts within one test pattern from three to two, (ii) ensuring the assumption of equipotential metal contacts used in modelling is more easily attained experimentally, and (iii) allowing the fabrication of reduced geometrical dimensions essential for determining low specific contact resistivity values. The analytical expressions are presented and experiment results are undertaken to demonstrate the accuracy of the technique. There are no error corrections required for determining contact parameters using the presented test structure.

The transport properties of the atomic scale side contact between different metals (Au, Ag, Pt, Cu, Ni, Pd) and graphene with open zigzag ends have been studied from first-principles electron transport calculations. According to the contact configurations, we find the weakly interacting metals (Au, Ag, Pt and Cu) can form chemical bonds at the open graphene’s atomic edges, while the strongly interacting ones form chemical bonds in the whole contact region. Comparing with the case of end contact which could effectively decrease the contact resistance, the atomic scale side contact shows better transport properties than the end contact. And the graphene/metal side contact with hydrogen terminated graphene edge show obviously large resistance than the ones with open graphene edge, which signifies the importance of the termination of graphene edge in graphene/metal contact.

In order to achieve high performance, the design of devices for large-area electronics needs to be optimized despite material or fabrication shortcomings. In numerous emerging technologies thin-film transistor (TFT) performance is hindered by contact effects. Here, we show that contact effects can be used constructively to create devices with performance characteristics unachievable by conventional transistor designs. Source-gated transistors (SGTs) are not designed with increasing transistor speed, mobility or sub-threshold slope in mind, but rather with improving certain aspects critical for real-world large area electronics such as stability, uniformity, power efficiency and gain. SGTs can achieve considerably lower saturation voltage and power dissipation compared to conventional devices driven at the same current; higher output impedance for over two orders of magnitude higher intrinsic gain; improved bias stress stability in amorphous materials; higher resilience to processing variations; current virtually independent of source-drain gap, source-gate overlap and semiconductor thickness variations. Applications such as amplifiers and drivers for sensors and actuators, low cost large area analog or digital circuits could greatly benefit from incorporating the SGT architecture.

A multi-scale modeling of electron transport via a metal-semiconductor interface is carried out by coupling ab initio calculations with three-dimensional finite element ensemble Monte Carlo simulations. The results for the Mo/GaAs (001) interface show that variations of the electronic properties with the distance from the interface have a strong impact on the transport characteristics. In particular, the calculated tunneling barrier differs dramatically from that of the ideal Schottky model of an abrupt metal-semiconductor interface. The band gap narrowing near the interface lowers resistivity by more than one order of magnitude: from 2.1×10-8 Ωcm² to 4.7×10-10 Ωcm². The dependence of the electron effective mass from the distance to the interface also plays an important role bringing resistivity to 7.9×10-10 Ωcm².

Understanding electron transfer in molecular systems is important, especially in the context of molecular electronics. With the desire to incorporate biological molecules in molecular electronic devices, there is a need to establish the relative importance of the various factors like the environment and the molecular structure (DNA sequence) on the electrical conduction. There has been much debate about mechanisms of electron transfer in biological molecules. We have conducted a systematic study of electron conduction across DNA molecular segments using the non-equilibrium Green function (NEGF) method. The Hamiltonian matrix elements were determined within the framework of the Extended Hückel Approximation. In considering (CG) base pair sequences, we find that the conductance decreases with segment length and that the substitution of (AT) base-pairs also reduces the conductance. When the DNA segments are in aqueous solution, the conductance is found to almost double in magnitude.

We present the fabrication of a high-temperature stable thermoelectric generator based on nanocrystalline silicon. Highly doped silicon nanoparticles were sintered by a current activated sintering technique to get nanocrystalline bulk silicon. The metalization of silicon was realized by (electro-)chemical plating and the specific electrical contact resistance ρc of the semiconductor-metal interface was measured by a transfer length method. Values as low as $\rho _C < 1 \cdot 10^{ - 6} \,\Omega cm^2 $ were measured. The metalized nanocrystalline silicon legs were sintered to metalized ceramic substrates using a silver-based sinter paste. The device figure of merit of the thermoelectric generator was determined by a Harman measurement with a maximum ZT of approximately 0.13 at 600 °C.

Sharper nanotips are required for application in nanoprobing systems due to a shrinking contact size with each new transistor technology node. We describe a two-step etching process to fabricate W nanotips with controllable tip dimensions. The first process is an optimized AC electrochemical etching in KOH to fabricate nanotips with a radius of curvature (ROC) down to 90 nm. This was followed by a secondary nanotip sharpening process by laser irradiation in KOH. High aspect ratio nanotips with ROC close to 20 nm were obtained. Finally we demonstrate the application of the fabricated nanotips for nanoprobing on advanced technology SRAM devices.