This chapter will offer an introduction to how jitter and phase noise are generated in the most common oscillator topologies. Starting with the treatment of basic circuits like a current charging a capacitor, or an inverter, we will continue by analyzing jitter and phase noise generation in ring, relaxation, and LC oscillators. Both linear time invariant and linear time variant approaches will be illustrated.

The chapter will finish with an overview of how jitter is “transformed” by two of the most common frequency processing circuits: a digital frequency divider and an ideal frequency multiplier.

Jitter in Basic Circuits

The next sections provide an explanation, both qualitative and quantitative, of how jitter manifests itself in basic oscillator circuits.

Noisy Current Charging a Capacitor

As mentioned already in Section 1.3, in integrated circuit design a central element is a current loading a capacitor. Digital gates, clock buffers, delay elements of relaxation and ring oscillators are just few examples of where this element can be found. Due to its ubiquity and importance, it is worth analyzing in some detail from the standpoint of jitter generation. In the following we will revisit the example provided in Section 1.3, and treat it with a complete mathematical analysis. The case of a PMOS transistor charging a capacitor is shown in Figure 4.1. The case of an NMOS discharging the capacitor is identical.

The goal of this analysis is to derive an expression for the variation of the time instant at which the charging voltage crosses a given threshold V0 (see Figure 4.1). The first step is to recognize that the resulting time deviation is due to two different components. The first is the effect of the noise current in injected into the capacitor by the PMOS during the charging transient. The second is due to the fact that, even if the capacitor is considered discharged at time zero, there is voltage noise present on it due to the circuitry which is used to keep it discharged. This noise can be considered as a random initial vertical offset which will affect the threshold crossing time.