In this chapter we analyze the effect of jitter on synchronous digital systems. We will first introduce the register (also known as flip-flop) as the central element of the design, its associated timing requirements, and the standard configuration for edge-triggered digital design. After analyzing the effect of jitter on the standard configuration, the reader will be introduced to the case of divided clock systems, enabled systems and multicycle systems. Finally, a section is dedicated to latch-based digital design and the effect of jitter on it.

Edge-Triggered Synchronous Design

In modern integrated systems, the vast majority of the digital functions are implemented in edge-triggered synchronous design. The central element of these systems is the register, a circuit which transfers to its output the digital value of its input, on the occurrence of the edge of a clock signal. Shown in Figure 5.1 is the symbol of a register and the corresponding timing waveforms. In an ideal register, when the rising edge of the clock signal CK occurs, the output Y assumes immediately the value of the input X at that particular instant. In practice, a register behavior differs from the ideal in at least three aspects. First, in order to be able to capture the input data correctly, the input data has to be stable some time before the rising edge of CK. This time is called setup time and is indicated by τsu. Second, the input data is not allowed to change its value for some time after the rising edge of CK. This time is called the hold time and is indicated by τho. Third, even if setup and hold time constraints are satisfied, there is a propagation delay from input to output, so that the new data appears at the output Y some time after the rising edge of CK. This time is typically called the clock-to-Q, and is indicated by τcq.

Figure 5.2 illustrates the typical configuration encountered in synchronous edgetriggered designs. A first register, or bank of registers, samples the incoming data X1 with the clock CK and produces the output Y1. This output is processed by a combinatorial logic network, and its result X2 is fed to the input of a second register, or bank of registers. The second register samples the processed data X2 with the same clock CK, and produces the output Y2.