In this chapter, first we describe the full-scan methodology, including example designs of scan flip-flops and latches, organization of scan chains, generation of test vectors for full-scan circuits, application of vectors via scan, and the costs and benefits of scan. This is followed by a description of partial scan techniques that can provide many of the benefits of full scan at lower costs. Techniques to design scan chains and generate and apply vectors so as to reduce the high cost of test application are then presented.

We then present the boundary scan architecture for testing and diagnosis of inter-chip interconnects on printed circuit boards and multi-chip modules.

Finally, we present design for testability techniques that facilitate delay fault testing as well as techniques to generate and apply tests via scan that minimize switching activity in the circuit during test application.

Introduction

The difficulty of testing a digital circuit can be quantified in terms of cost of test development, cost of test application, and costs associated with test escapes. Test development spans circuit modeling, test generation (automatic and/or manual), and fault simulation. Upon completion, test development provides test vectors to be applied to the circuit and the corresponding fault coverage. Test application includes the process of accessing appropriate circuit lines, pads, or pins, followed by application of test vectors and comparison of the captured responses with those expected.