Crossref Citations
This Book has been
cited by the following publications. This list is generated based on data provided by Crossref.
Zhigang Jiang
and
Gupta
2003.
A test generation approach for systems-on-chip that use intellectual property cores.
p.
278.
Gupta, P.
Rui Zhang
and
Jha, N.K.
2004.
An automatic test pattern generation framework for combinational threshold logic networks.
p.
540.
Veneris, A.
Chang, R.
Abadir, M.S.
and
Amiri, M.
2004.
Fault equivalence and diagnostic test generation using ATPG.
p.
V-221.
Moayad Fahim Ali
Veneris, A.
Safarpour, S.
Abadir, M.
Drechsler, R.
and
Smith, A.
2004.
Debugging sequential circuits using Boolean satisfiability.
p.
44.
Safarpour, S.
Veneris, A.
Drechsler, R.
and
Lee, J.
2004.
Managing don't cares in Boolean satisfiability.
p.
260.
Fahim Ali, M.
Veneris, A.
Smith, A.
Safarpour, S.
Drechsler, R.
and
Abadir, M.
2004.
Debugging sequential circuits using Boolean satisfiability.
p.
204.
Smith, A.
Veneris, A.
and
Viglas, A.
2004.
Design diagnosis using Boolean satisfiability.
p.
218.
Smith, A.
Veneris, A.
Ali, M.F.
and
Viglas, A.
2005.
Fault diagnosis and logic debugging using Boolean satisfiability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 24,
Issue. 10,
p.
1606.
Schuchman, E.
and
Vijaykumar, T.N.
2005.
Rescue: A Microarchitecture for Testability and Defect Tolerance.
p.
160.
Wang, L.T.
Xiaoqing Wen
Po-Ching Hsu
Shianling Wu
and
Guo, J.
2005.
At-speed logic BIST architecture for multi-clock designs.
p.
475.
Tseng, W.-D.
2005.
Scan chain ordering technique for switching activity reduction during scan test.
IEE Proceedings - Computers and Digital Techniques,
Vol. 152,
Issue. 5,
p.
609.
Pradhan, D.K.
and
Chunsheng Liu
2005.
EBIST: a novel test generator with built-in fault detection capability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 24,
Issue. 9,
p.
1457.
Veneris, Andreas
Chang, Robert
Abadir, Magdy S.
and
Seyedi, Sep
2005.
Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG.
Journal of Electronic Testing,
Vol. 21,
Issue. 5,
p.
495.
Lingappan, L.
and
Jha, N.K.
2005.
Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits.
p.
418.
Arora, V.
and
Sengupta, I.
2005.
A Unified Approach to Partial Scan Design using Genetic Algorithm.
p.
414.
Liu, J.B.
and
Veneris, A.
2005.
Incremental fault diagnosis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 24,
Issue. 2,
p.
240.
Qiang Qiang
Chia-Lun Chang
Saab, D.G.
and
Abraham, J.A.
2005.
Case study of ATPG-based bounded model checking: verifying USB2.0 IP core.
p.
461.
Chien-Mo Li, J.
2005.
Diagnosis of single stuck-at faults and multiple timing faults in scan chains.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
Vol. 13,
Issue. 6,
p.
708.
Sandireddy, R.K.K.R.
and
Agrawal, V.D.
2005.
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits.
p.
1014.
Yung-Chieh Lin
Feng Lu
and
Kwang-Ting Cheng
2005.
Accurate diagnosis of multiple faults.
p.
153.