The problem of determining whether a digital circuit operates correctly is of both theoretical interest and practical concern. Present-day digital systems may be disabled by almost any internal failure. Failures are caused by faults that are initially manifested as errors and finally as failures. In this chapter, we shall study various fault models, techniques for generating tests, and logic synthesis techniques that ensure testability with respect to various types of fault.

Fault models

In order to alleviate the complexity of test generation, one needs to model the actual defects that may occur in a chip with fault models at higher levels of abstraction. This process of fault modeling considerably reduces the burden of testing because it obviates the need for deriving tests for each possible defect. This is due to the fact that many physical defects map to a single fault at the higher level.

Faults may change the logic values at some internal lines in the integrated circuit, or they may result in a change in the voltage or current levels. They may also change the temporal behavior of the circuit.

Currently, most popular fault models are described at the structure and switch levels of the integrated-circuit design hierarchy. In this section, we shall examine these fault models.

Structural fault models

In structural testing we need to make sure that the interconnections in the given structure are fault-free and are able to carry both 0 and 1 signals. The stuck-at fault model is directly derived from these requirements.