Book contents
- Frontmatter
- Contents
- Foreword
- Preface
- List of Abbreviations
- List of Symbols
- 1 Introduction
- 2 Review on Modeling Junctionless FETs
- 3 The EPFL Charge-based Model of Junctionless Field-Effect Transistors
- 4 Model-Driven Design-Space of Junctionless FETs
- 5 Generalization of the Charge-based Model: Accounting for Inversion Layers
- 6 Predicted Performances of Junctionless FETs
- 7 Short-Channel Effects in Symmetric Junctionless Double-Gate FETs
- 8 Modeling AC Operation in Symmetric Double-Gate and Nanowire JL FETs
- 9 Modeling Asymmetric Operation of Double-Gate Junctionless FETs
- 10 Modeling Noise Behavior in Junctionless FETs
- 11 Carrier Mobility Extraction Methodology in JL and Inversion-Mode FETs
- 12 Revisiting the Junction FET: A Junctionless FET with an ∞ Gate Capacitance
- 13 Modeling Junctionless FET with Interface Traps Targeting Biosensor Applications
- Appendix A Design-Space of Twin-Gate Junctionless Vertical Slit FETs
- Appendix B Transient Off-Current in Junctionless FETs
- Appendix C Derivatives of Mobile Charge Density with Respect to V GS and V DS
- Appendix D Global Charge Density at Drain in Depletion Mode
- Appendix E Global Charge Density at Drain in Accumulation Mode
- Appendix F The EPFL Junctionless MODEL
- References
- Index
8 - Modeling AC Operation in Symmetric Double-Gate and Nanowire JL FETs
Published online by Cambridge University Press: 24 February 2018
- Frontmatter
- Contents
- Foreword
- Preface
- List of Abbreviations
- List of Symbols
- 1 Introduction
- 2 Review on Modeling Junctionless FETs
- 3 The EPFL Charge-based Model of Junctionless Field-Effect Transistors
- 4 Model-Driven Design-Space of Junctionless FETs
- 5 Generalization of the Charge-based Model: Accounting for Inversion Layers
- 6 Predicted Performances of Junctionless FETs
- 7 Short-Channel Effects in Symmetric Junctionless Double-Gate FETs
- 8 Modeling AC Operation in Symmetric Double-Gate and Nanowire JL FETs
- 9 Modeling Asymmetric Operation of Double-Gate Junctionless FETs
- 10 Modeling Noise Behavior in Junctionless FETs
- 11 Carrier Mobility Extraction Methodology in JL and Inversion-Mode FETs
- 12 Revisiting the Junction FET: A Junctionless FET with an ∞ Gate Capacitance
- 13 Modeling Junctionless FET with Interface Traps Targeting Biosensor Applications
- Appendix A Design-Space of Twin-Gate Junctionless Vertical Slit FETs
- Appendix B Transient Off-Current in Junctionless FETs
- Appendix C Derivatives of Mobile Charge Density with Respect to V GS and V DS
- Appendix D Global Charge Density at Drain in Depletion Mode
- Appendix E Global Charge Density at Drain in Accumulation Mode
- Appendix F The EPFL Junctionless MODEL
- References
- Index
Summary
In addition to analytical DC models of junctionless FETs, the design of analog and digital circuits requires accurate modeling of AC characteristics as well. Adopting the charge–voltage relationships presented in Chapter 3, a complete analytical model for transcapacitances valid in all regions of operation is derived for double-gate and nanowire junctionless FETs here.
The charge-based model presented in Chapter 3 covers depletion and accumulation modes. However, at flat-band the derivative of the charge densities with respect to the potential equals, exceeding the theoretical value (but continuity of the charge and derivatives is still preserved). This mismatch around the flat-band prevents obtaining accurate derivatives of the mobile charge density with respect to the applied voltages. In addition, as soon as is increased, the nonuniformity of the channel must also be taken into account to evaluate the equivalent charge densities on the different nodes. Here, a detailed treatment of the charges distribution and partitioning scheme inside the channel of junctionless FETs is given and used to derive a complete small signal-equivalent circuit.
Transcapacitance Matrix in Symmetric Double-Gate FETs
A general analysis of transadmittances is reviewed for symmetric double-gate fieldeffect transistors (see Figure 8.1), no matter the principle of operation (inversion, accumulation, and depletion). The inherent symmetry and the lack of a bulk reference for these architectures results in some unique properties of the matrix transadmittance.
In a harmonic analysis, small-signal current and voltages and are linearly dependent through the so-called Y-matrix transadmittance:
This Y-matrix can be split into two parts: a real number contribution dealing with conductances (matrix conductance) for the in-phase response of the signal and an imaginary number contribution dealing with capacitances for the out-phase contribution (capacitance matrix) (j denotes the imaginary unit and the angular frequency). For a typical MOSFET device with four terminals, gate (g), drain (d), source (s), and body (b), the and matrices have the following elements:
where the element represents the in-phase current response at node i upon a (small) voltage change at node j, which is a transconductance.
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- Publisher: Cambridge University PressPrint publication year: 2018