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Nanoporous devices constitute emerging platforms for selective molecule separation and sensing, with great potential for high throughput and economy in manufacturing and operation. Acting as mass transfer diodes similar to a solid-state device based on electron conduction, conical pores are shown to have superior performance characteristics compared to traditional cylindrical pores. Such phenomena, however, remain to be exploited for molecular separation. Here we present performance results from silicon membranes created by a new synthesis technique based on interferometric lithography. This method creates millimeter sized planar arrays of uniformly tapered nanopores in silicon with pore diameter 100 nm or smaller, ideally-suited for integration into a multi-scale microfluidic processing system. Molecular transport properties of these devices are compared against state-of-the-art polycarbonate track etched (PCTE) membranes. Mass transfer rates of up to fifteen-fold greater than commercial sieve technology are obtained. Complementary results from molecular dynamics simulations on molecular transport are reported.
We show heteroepitaxial growth of GaAs on Ge/SiGe grown on nanometer-scale grating structures. Conventional lithography techniques were combined with reactive ion and wet-chemical etching to fabricate 1-D patterns of silicon posts. The quality of the GaAs layers was investigated using high-resolution x-ray diffraction (HRXRD), transmission electron microscopy (TEM), scanning electron microscopy (SEM), photoluminescence (PL) and etch pit density (EPD) measurements. Our results show significant improvement in the quality of heteroepitaxial layers grown on nano patterned structures compared to those on the unpatterned silicon. The optical quality of the GaAs/Ge/SiGe on nano-scale patterned silicon was comparable to that of single crystal GaAs.
We report highest quality Ge epilayers on nanoscale patterned Si structures. 100% Ge films of 10 μm are deposited using chemical vapor deposition. The quality of Ge layers was examined using scanning electron microscopy (SEM), transmission electron microscopy (TEM), and high-resolution x-ray diffraction (HRXRD) measurements. The defect density was evaluated using etch pit density measurements. We have obtained lowest dislocation density (5×105 cm-2) Ge films on the nanopatterned Si structures. The full width half maximum peaks of the reciprocal space maps of Ge epilayers on the nanopatterned Si showed 93 arc sec. We were able to get rid of the crosshatch pattern on the Ge surface grown on the nanopatterned Si. We also showed that there is a significant improvement of the quality of the Ge epilayers in the nanopatterned Si compared to an unpatterned Si. We observed nearly three-order magnitude decrease in the dislocation density in the patterned compared to the unpatterned structures. The Ge epilayer in the patterned Si has a dislocation density of 5×105 cm-2 as compared to 6×108 cm-2 for unpatterned Si.
A model was developed to calculate the elastic fields, including strain energy density, in multilayers grown epitaxially on a planar substrate. This model works well for compliant and non-compliant substrates. In particular we illustrate the model for four layer heterostructure and apply it for graded Ge (SixGe1−x) grown on a planar silicon substrate. Using the equations for static equilibrium and Hooke's law for isotropic materials under a plane stress condition, the elastic fields associated with each layer were calculated. The strain partitioning in this model reduces to the limiting case of a two- layer structure available in the literature. As it turns out here, strain partitioning is a function of the bulk unstrained lattice parameters, elastic constants and thicknesses of the layers. The model was qualitatively verified by comparing the strain energy density with the dislocation density away from a relatively thick substrate. This model helps shed some light on the factors important in achieving defect free multilayers for optoelectronic devices.
We describe novel 2-D structures that facilitate strain relief and allow us to obtain Ge epilayers that are free of defects. These structures can potentially absorb thermal expansion and lattice expansion mismatch as well as enable liftoff of heteroepitaxial layers for subsequent wafer reuse. Conventional lithography techniques were combined with reactive ion and wet-chemical etching to fabricate 2-D patterns of silicon posts. The dimensions of the posts were varied keeping the pitch (center to center distance) constant. Heteroepitaxial growth of Ge/SixGe1−x on these micrometer-scale structures was investigated. While, keeping the growth parameters constant, the geometry of the structures was varied to determine the optimum configuration for the highest quality heteroepitaxial growth. The quality of the Si1−xGex buffer system was investigated using high-resolution x-ray diffraction. Transmission electron microscopy (TEM) was used to analyze the epilayer cross-sections. Surface morphology was analyzed using scanning electron microscopy (SEM), atomic force microscopy (AFM) and optical microscopy. Our results show that the quality of the heteroepitaxial layers improves as the width of the posts in the 2-D pattern was decreased.
Observations of efficient room temperature photoluminescence (PL) from porous Si have generated a great deal of interest in the optical properties of nm-scale Si structures. The stochastic character of porous-Si fabrication results in a distribution of crystal sizes and shapes. We report on a scalable (to large areas) and manufacturable (to high volumes) fabrication technology for uniform, nm-linewidth Si structures providing an important testbed for controlled studies of these optical properties. Large areas ( ∼ 1 cm2) of extreme sub-μm structures (to ∼ 5 nm) are re-producibly fabricated. Both walls (1-D confinement) and wires (2-D confinement) are reported. The fabrication process includes: interferometric lithography, highly anisotropic KOH etching, and structure dependent oxidation. For the walls, nearly perfect <111> crystal planes form the sidewalls and very high width/depth aspect ratios (> 50) have been achieved. Raman scattering results on the walls demonstrate three regimes: 1) lineshapes and cross sections similar to bulk Si for line widths, W > 200 nm; 2) electromagnetic resonance enhancement of the cross section ( to - 100x) for W from 50-200 nm; and 3) highly asymmetric lineshapes and splittings from W < 30 nm. Photoluminescence is observed for the thinnest samples (W < 10 nm) and is as intense as that observed from porous Si with a spectral linewidth ∼ 50 % smaller than that of porous Si.
A non-contact temperature measurement technique based on diffraction-analysis monitoring of the thermal expansion of materials is discussed. Due to the need for noncontact temperature measurements during semiconductor processing, silicon was chosen for this demonstration. The diffraction method requires a grating of suitable spatial frequency etched on the surface of the silicon wafer. The diffraction angle from the grating depends on the grating period which varies with temperature. Two symmetrically disposed incident beams are used to provide a differential measurement which is relatively independent of sample tilt. A computer system is used to monitor the diffraction order movement, from the order separation a relative temperature change can be calculated in near real-time. Temperature sensitivity for the diffraction technique is inversely dependent on the grating length (number of lines) and independent of the grating width. A sensitivity of 0.75°C is demonstrated for a 3-mm wide grating over a 20-700°C temperature range.
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