This paper reports on characterization of the surface coverage of particles by in-situ lateral friction force measurement during chemical mechanical polishing. The lateral friction force apparatus was made to operate close to real CMP conditions. For these experiments a sapphire wafer of constant surface roughness was used. For both 2psi and 4psi down force we observed increase in lateral friction forces with increasing solid loading. The lateral friction forces have been found to be significantly dependent on the contact area at the wafer-pad-slurry interface, thus showing that in-situ dynamic friction force changes in the surface coverage of particles. From these results, we conclude that the enhancement of frictional force is due to increased contact area at the wafer-pad-slurry interfaces. The lateral friction force measurement can provide an understanding of wafer-pad-slurry interactions.

This paper describes CMP challenges in development of copper-low k process technology. As copper/oxide or copper/FSG backend schemes are being implemented successfully in early manufacturing, development focus has shifted to Cu/OSG (organo-silicate glass) integration development. Cu-OSG presents unique challenges with CMP integration, as these films tend to have much lower hardness than silicon dioxide. Significant process challenges have to be overcome prior to successfully implementing CMP process which does not mechanically damage the softer films and at the same time can achieve planarization requirements expected from CMP process. In addition, the OSG films tend to be hydrophobic leading to a need for developing improved cleaning processes/consumables. It was determined that Applied Materials ElectraPolishTM barrier slurry is extendable to OSG films. Good removal rate and removal profile can be achieved with ElectraPolishTM slurry. A proprietary cleaning solution reduced defect counts by 2 orders of magnitude as detected by SurfScan SS6200 on blanket OSG wafers. The same cleaning solution can be applied to copper/low-k patterned damascene wafers to clean both copper and dielectric surface. Polished OSG films have RMS roughness less than 2 angstroms and copper surface roughness about 5 angstroms with good surface finish. Blanket and patterned wafer results are presented to demonstrate final capability. Future directions for process enhancement are suggested.

Chemical Mechanical Planarization (CMP) occurs at an atomic level at the slurry/wafer interface and hence slurries and polishing pads play a critical role in the successful implementation of this process. Surface roughness, visco-elastic properties, thickness and pore size also play an important role in this process. Unfortunately the mechanical properties of polyurethane polishing pads used in CMP are poorly understood. Here we have studied the mechanical and visco-elastic properties and surface morphology of CMP pads using nano-indentation and dynamic mechanical analysis along with high resolution scanning electron microscopy. A state-of-the-art Universal Micro-Tribometer was used to measure the pad deformation behavior under load. A novel non-destructive scanning ultrasonic transmission technique was also used to characterize inhomogeneity of the visco-elastic properties of full-size CMP pads. Results obtained by different techniques were analyzed to demonstrate methods for quick and reliable evaluation of pad quality for current CMP technology.

Simulation of chemical-mechanical polishing is important because the chip-level planarity are difficult to control. The simulator has been developed for predicting and optimizing the thickness distribution after the STI and damascene CMP as well as ILD CMP using chip-level pattern density, elastic spring model and erosion model. In this study, the results of CMP simulation is shown to agree well with the measured data. The simulator can be used to optimize CMP process conditions and to generate design rules for filling dummy patterns which are used to improve the planarity and uniformity.

MESA is a feature-scale planarization model that predicts the changing topography of the wafer surface during the chemical mechanical polishing (CMP) process used in IC manufacturing. This model has previously been applied to the polish of inter-level dielectrics and copper. The present study is part of a model validation procedure for shallow trench isolation (STI) using experimental feature-scale data. It was carried out using the SpeedFam-IPEC Auriga polisher with SKW Associates 200-mm wafers (SKW3 MIT-STI-mask), Rodel IC 1000/1400 pads and Cabot SS-12 slurry. MESA accounts for observed differences in planarization using Rodel IC1000 with and without foam backing as well as the pattern-density dependence within each die. The data were obtained and plotted in such a way that the active-area and trench-oxide levels are displayed throughout the whole polish, including the points where active area clears to nitride and silicon as well as where trench oxide dishes below the silicon level. The pattern density effect is evident in both cases, but a comparison between the two pads shows less pattern density effect and improved planarization with the single IC 1000 pad.

MESA is shown to predict the details of the topographical evolution for STI CMP on the feature scale. When validated by fitting the pad constants k1 and k2 to describe the planarization, MESA provides reasonably accurate predictions for the polish of any oxide pattern structure as long as the same CMP process is used.

Test mask for characterizing pattern dependent variation of the remaining thickness after chemical-mechanical polishing (CMP) was designed with taking the experimentally obtained interaction distance into consideration. Measured interaction distance was constant independent of pattern variables such as pattern density and pattern shapes between line and area. And systematic exploration regarding pitch effects on remaining nitride thickness in STI (Shallow Trench Isolation) CMP was performed with comparing PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate) and HDP (High Density Plasma) oxide. Both measured remaining nitride thickness and expected oxide pattern density from consideration of deposition profile effects showed a good correlation with respect to pitch variation for a constant layout pattern density.

Sentinelä is an optical multiprobe endpoint detection (EPD) system that has been developed by SpeedFam-IPEC (SFI) for the 200-mm and 300-mm Momentum orbital polishers. Sentinel EPD for copper CMP is based on monitoring the visible spectrum of light from a Xenon (Xe) flash lamp, which has been reflected by the wafer surface during polish. Large representative areas of the wafer are monitored from multiple locations in the pad continuously throughout the polish process. Spectra of reflected light from cleared and uncleared copper on a pattern wafer demonstrate a clear transition from copper to the underlying dielectric layer.

With the Sentinel EPD system, the wafer is probed at optimized multiple locations constantly throughout the polish process by small-diameter light spots. The coverage of the monitoring is extensive and the radial coverage is substantial on a real-time basis. The EPD call is made based on an EPD signal, which displays the fractional copper coverage as a function of polish time. The detection of copper clearing on the SFI Momentum tools is very reliable and predictable, and not sensitive to process changes.

A pattern specific corrosion of aluminum wires was found during aluminum chemical mechanical polishing process. This paper presents and discusses the particular pattern dependency of the corrosion behavior and effective control methods in order to reduce the corrosion. An aluminum single damascene structure on silicon dioxide thin film was prepared and the effects of process variables and pattern configuration on corrosion behavior were extensively explored. The corrosion behavior was quantitatively analyzed using sheet resistance of corroded line. It was demonstrated that corrosion of aluminum wire was associated with cleaning media and pattern configuration. The area ratio between sub-micron size line and pads was the most important factors to determine the corrosion behavior. A post cleaning chemical including corrosion inhibitor couldn't prevent the corrosion perfectly. It was found that sacrificial dummy lines could reduce the aluminum corrosion, which suggests that the aluminum corrosion could be controlled by the structural consideration in aluminum damascene.

CMP slurry with inorganic/resin abrasive was investigated for the Al/low k damascene wiring. [1] The slurry showed less scratching, higher polishing rate and better planarity. These advantages are attributable to the elasticity of the resin. The soft resin particle behaves as a cushion and prevents the scratching caused by agglomerated inorganic particles and foreign material. The springy feature of the resin particle increases the selectivity of removal rate at convex portions and concave portions. Furthermore, the pressure is loaded to the Al film surface effectively through the resin particle and higher CMP rate can be achieved even without chemicals such as oxidizers and acids. [2] This chemical free polishing would be the advantageous for preventing the corrosion of Al.

Wepropose an integratedcontact mechanics and density-step-heightmodel of pattern dependencies for the chemical-mechanical polishing (CMP) of multi-level copper interconnects, and show preliminary comparisons with experimental data for the overburden copper removal stage. The model uses contact mechanics to correctly apportion polishing pressure on all sections of an envelop function that reflects the long-range thickness differences on the chip, or region of interest. With the pressure over the entire envelop known, the density-step-height part of the model is then used to compute the amount of material removed in the local “up-areas” and “down-areas”. ThismodelshowspromiseinaccuratelyandefficientlypredictingpostCMPcopperanddielectric thicknesses across an entire chip.

Nanotopography refers to 10-100 nm surface height variations that exist on a lateral millimeter length scale on unpatterned silicon wafers. Chemical mechanical polishing (CMP) of deposited or grown films (e.g., oxide or nitride) on such wafers can generate undesirable film thinning which can be of substantial concern in shallow trench isolation (STI) manufacturability. Proper simulation of the effect of nanotopography on post-CMP film thickness is needed to help in the measurement, analysis, diagnosis, and correction of potential problems.

Our previous work has focused on modeling approaches that seek to capture the thinning and post-CMP film thickness variation that results from nanotopography, using different modeling approaches. The importance of relative length scale of the CMP process used (planarization length) to the length scale of the nanotopography on the wafer (nanotopography length) has been suggested.

In this work, we report on extensive experiments using sets of 200 mm epi wafers with a variety of nanotopography signatures (i.e., different nanotopography lengths), and CMP processes of various planarization lengths. Experimental results indicate a clear relationship between the relative scales of planarization length and nanotopography length: when the planarization length is less than the nanotopography length, little thinning occurs; when the CMP process has a larger planarization length, surface height variations are transferred into thin film thickness variations. In addition to presenting these experimental results, modeling of the nanotopography effect on dielectric CMP processes is reviewed, and measurement data from the experiments are compared to model predictions. Results show a good correlation between the model prediction and the experimental data.

It has recently been reported that some waviness may affect STI CMP yield. CMP is designed primarily to planarize relatively with large r scale than small topography. However, there may be a range of wafer topographies in which STI patterns are over-polished, depending on peak-to-valley variations and frequencies. Permissible peak-to-valley variations and frequencies are calculated by determining whether the difference in polish quantities between the peak and valley is less than permissible values, such as 10 nm, 20 nm, and 30 nm. Reports indicate that slurry selectivity can decrease this effect, although with certain disadvantages.

Polyurethane polishing pads are commonly used for chemical-mechanical polishing (CMP) of semiconductor wafers. Structural, chemical, and mechanical property changes of the polishing pads due to CMP are examined. Tungsten and oxide film layers are polished from the wafer surface using the polishing pad and abrasive slurry system. The polishing pad surface is flattened with polishing, and hence, reducing the effective area for slurry transport. The abrasive is used for abrading off the film from the surface. W, Al, I, and K accumulate in the polishing pad after tungsten CMP and Si accumulates after oxide CMP. Material accumulates in the pad pores and grooves. Electron Microprobe X-ray Analysis and Wavelength Dispersive Spectrometry (WDS) were used to examine the changes across the thickness of the pad. Fourier Transform Infrared Spectroscopy (FTIR) was used to determine the changes to the polyurethane isocyanate group. The reduction in the isocyanate group and increase in the hydroxyl group after tungsten CMP indicates that a hydrolysis reaction of the isocyanate to form carboxylic acid occurs.

A Trench isolation technology has been developed and applied to high-speed bipolar LSI production. In general, the wafer surface after a conventional ploy-Si Chemical-Mechanical-Polishing (CMP) is contaminated with silica particles and chemical impurities. These contaminations produce some unexpected patterns and crystal defects in the wafer surface layer after oxidation. It is difficult to remove them by the conventional cleaning techniques. Therefore, we have established the new post CMP cleaning method, using the electrolytic ionized water containing chemical additive of a small quantity. The anode water has the cleaning effect for the metallic and organic contaminations, and the cathode water has the removing effect for the particles and the etching effect for the poly-Si surface. For this new cleaning process, it is important to avoid the chemical mechanical damages on the surface and to control the surface roughness. Our experimental work has been focused on the large numbers of the remaining particle and the surface roughness using a particle counter and an atomic force microscopy (AFM). We herein report the properties of the electrolytic ionized water and the examined results of poly-Si surface after CMP process. It was found that the electrolytic ionized water is effective for surface control, and the new cleaning process is useful for CMP process.

The introduction of Chemical Mechanical Polishing (CMP) into semiconductor device processing brought a significant need for wet chemistry research and development in this industry. With the transition from aluminum to copper for advanced interconnect metallization came a tremendous amount of electrochemical research and process development towards a production worthy copper CMP process capable of meeting the stringent specifications of dual damascene integration.In addition, the dual damascene integration scheme introduced copper deposition challenges that brought significant activity in developing another wet chemistry process, electroplating. These two sequential, chemical processes have been shown to have significant interaction that has created significant challenges in process integration.

A present semiconductor cleaning technology is based upon RCA cleaning technology which consumes vast amounts of chemicals and ultra pure water(UPW) and is the high temperature process. Therefore, this technology gives rise to the many environmental issues, and some alternatives such as functional water cleaning are being studied. The electrolyzed water was generated by an electrolysis system which consists of anode, cathode, and middle chambers. Oxidative water and reductive water were obtained in anode and cathode chambers, respectively. In case of NH4Clelectrolyte, the oxidation-reduction potential and pH for anode water(AW) and cathode water(CW) were measured to be +1050mV and 4.8, and -750mV and 10.0, respectively. AW and CW were deteriorated after electrolyzed, but maintained their characteristics for more than 40 minutes sufficiently enough for cleaning. Their deterioration was correlated with CO2 concentration changes dissolved from air. It was known that AW was effective for Cu removal, while CW was more effective for Fe removal. The particle distributions after various particle removal processes maintained the same pattern. In this work, RCA consumed about 9 chemicals, while EW did only 400ml HCl electrolyte or 600ml NH4Cl electrolyte. It was hence concluded that EW cleaning technology would be very effective for eliminating environment, safety, and health(ESH) issues in the next generation semiconductor manufacturing.

This paper reports on the effect of colloidal abrasive particle size in the polishing of thermally grown silicon dioxide on 100mm diameter, P-type, (100), single crystal silicon wafers. The abrasive particle sizes were varied in six (6) slurries with pH values of 10.97 ± 0.08. The abrasive sizes were 10, 20, 50, 80, 110 and 140nm in diameter, and the slurry contained 30 weight percent abrasives. The experimental results indicate that the material removal rate (MRR) varies with the volume of the particle size. Results also confirm that there exists an optimum abrasive particle size with respect to material removal rate and surface finish. For a pad surface roughness of 5.2μm (Ra), the slurry containing 80nm particles resulted in the highest material removal rate and best surface finish. A nano-film model based on the pad roughness is used to explain the results.

This paper attempts to establish planarization model in chemical mechanical polishing of silicon oxide using high selective ceria slurry. Though removal rate of the high area is increased due to a high pressure focused on the area with abrasive and pad, the removal rate of the same area is not increased but decreased even in the very beginning of polishing with ceria slurry. It also observed that only the elevated area is polished and dishing is not occurred during the polishing in high selective ceria CMP. In this work, it is proposed that ceria abrasives are filled in the low trench area and then support the pad as well as high area during the CMP, which results in planarization without dishing.

Chemical-mechanical polishing (CMP) involves complex mechanical and chemical interactions between a rough elastomeric pad, the wafer being polished and an abrasive slurry containing sub-micron diameter silica particles. The interaction between these abrasive particles and the wafer surface and their impact upon material removal rates is still unclear. Particle dynamics in a model CMP geometry are studied experimentally in this work. Only the particles that actually interact with, and presumably polish, the model wafer surface are visualized using total internal reflection fluorescence (TIRF). The effect of process properties such as particle diameter, particle material, pad-wafer separation and shear rate upon the particle concentration immediately adjacent to the wafer surface is investigated.