Porous methylsilsesquioxane (p-MSQ) films (JSR LKD 5109) were treated with alkyldimethylmonochlorosilanes having chain lengths of one, four, and eight carbon atoms dissolved in supercritical carbon dioxide at 150-300 atm and 50-60°C to repair oxygen ashing damage. Fourier transform infrared (FTIR) spectroscopy showed that trimethylchlorosilane (TMCS), butyldimethylchlorosilane (BDMCS), and octyldimethylchlorosilane (ODMCS) reacted with silanol groups on the surfaces of the pores producing covalent Si-O-Si bonds. Selfcondensation between alkylsilanols produced a residue on the surface, which was partially removed using a pure scCO2 rinse. The hydrophobicity of the blanket p-MSQ surface was recovered after silylation treatment as shown by contact angles >85°. The initial dielectric constant of 2.4 ± 0.1 increased to 3.5 ± 0.1 after oxygen plasma ashing and was reduced to 2.6 ± 0.1 by TMCS, 2.8 ± 0.1 by BDMCS, and 3.2 by ODMCS.

Optical waveguides for three-dimensionally stacked chip fabrication technologies, in which optical connection between layers plays a central role, are described. CMOS-compatible approaches to optical via and waveguide fabrication are addressed. Detailed modeling is used for design optimization and also addresses how manufacturing variations from ideal design may affect device performance.

Textural evolution of Cu interconnects having a different line width was investigated after annealing. Texture was measured on the surface of Cu interconnects using EBSD (electron backscattered diffraction) techniques including GBCD (grain boundary character distribution). To analyze a relationship between the stress distribution and textural evolution in the samples investigated, the micro stresses were calculated for the different line width at 200°C using FEM (finite element modeling). In this investigation, it was found that the inhomogeneity of stress distribution in Cu interconnects is an important factor is necessary for understanding textural transformation after annealing. A new interpretation of textural evolution in damascene interconnects lines after annealing is suggested, based on the state of stress and the growth mechanisms of Cu electrodeposits.

The effect of moisture and aqueous solution chemistry on the rate of crack growth in lithographically patterned arrays of copper and low dielectric constant (LKD) materials is reported. Crack growth in the direction orthogonal to the features is demonstrated to fail at significantly increased loads compared to parallel cracking. Decreasing feature width is also shown to increase the structures resistance to fracture, particularly at reduced loads. The chemical interactions and mechanisms of energy dissipation are discussed.

In this work, the adhesion of CVD dielectric caps to ULK MSQ spin-on dielectric materials with k values of 2.2 and 2.0, and a ULK CVD material with a k value of 2.7 is presented. A substantial improvement in cap adhesion to both the k2.2 ULK MSQ and the k2.7 ULK CVD material is demonstrated. The improvement is obtained using a low-k CVD glue material between the ULK dielectric and the subsequent cap material and/or by optimizing the CVD cap film deposition. Four-point bend measurement of adhesion strength is used to quantify the improvement in interface adhesion. The improvement in CVD cap adhesion is demonstrated to be strongly dependent upon both the glue layer film and the cap deposition conditions. While optimization of the CVD cap materials results in adequate adhesion for the k2.2 ULK MSQ, these improvements are demonstrated not to extend to the k2.0 ULK MSQ film.

This work is aimed at understanding the nature of the interactions between metal interconnects and nanoporous dielectrics in integrated circuits. Electrical testing of MIS capacitors is used to assess Cu diffusion and charge injection in the dielectric in the presence of an electric field. We have found that surface modification of nanoporous silica reveals the importance of chemically bound or adsorbed water species in the dielectric and how they trigger metal diffusion. We propose that a combination of moisture-related species in the dielectric and interfacial oxygen oxidize Cu. The copper oxide acts as a source for Cu ions available for diffusion. A quantitative analysis of Cu drift in nanoporous dielectrics that shows the importance of surface chemistry is presented and the mechanism of metal diffusion and charge injection in nanoporous dielectrics is discussed.

Numerical simulations of thermal stresses in copper interconnect and low-κ dielectric systems are carried out. The analyses include two- and three-dimensional finite element modeling of the interconnect structure. Various combinations of metal, oxide and polymer-based low-κ dielectric schemes are considered in the simulation. The evolution of stresses and deformation pattern in copper, barrier layers, and the dielectrics are critically assessed.

Cross-section nano-indentation is a technique that consists of cleaving a wafer, indenting behind the stack on the side surface causing delamination, and measuring the delaminated area in an optical microscope. It is shown to be a reliable rapid technique for adhesion evaluation and process optimization of the SiO2/barrier/copper stack.

Ternary W-Si-N thin films have been reactively sputter-deposited from a W5Si3 target at different nitrogen partial pressures. The composition has been determined by 2.2 MeV4He+ beam, the structure by x-ray diffraction and transmission electron microscope, the chemical bonds by Fourier transform - infrared spectroscopy and the surface morphology by scanning electron microscopy. Electrical resistivity was measured by four point probe technique on the as grown films. The film as-deposited is amorphous with the Si/W ratio increasing from about 0.1 up to 0.55 with the nitrogen content going from 0 to 60 at%. The heat treatments up to 980 °C induce a loss of nitrogen in the nitrogen rich samples. Segregation of metallic tungsten occurs in the sample with low nitrogen content (W58Si21N21). Samples with high nitrogen content preserve the amorphous structure, despite of the precipitation of a more ordered phase inferred by FT-IR absorbance spectrum of the layer treated at highest temperature. The surface morphology depends upon the nitrogen content; the loss of nitrogen induces the formation of blistering and in the most nitrogen rich sample the formation of holes. Electrical resistivity preliminary results on the as grown layers range between 500 and 4750 μωcm passing from the lowest to the highest N concentration.

A process oriented approach is demonstrated for modeling the stress evolution during the entire back end process flow. No ad hoc assumptions regarding stress states are made for layer deposition and etching. Intrinsic stresses from material formation, thermal mismatch stresses from temperature ramps, stress relaxation due to viscous deformation, and stress profile redistribution upon deposition and etching are all considered at each process. Parametric studies are carried out to examine the effects of viscous flow, material selection and layout variations. It is found that the viscous flow of the passivation and dielectric materials have large impact on stress evolution. A TCAD assisted design approach is suggested for lowering stress levels of critical stress components. The implications of the stress modeling results on reliability issues like stress-triggered void formation are discussed.

The thermal stability and electrical resistivity of Ag(Al) alloy thin films on SiO2 are investigated and compared to pure Ag thin films by performing various analyses: Rutherford backscattering spectrometry (RBS), X-ray diffractometry (XRD), transmission electron microscopy (TEM), and four-point probe. The susceptibility to agglomeration of Ag on SiO2 layer is a drawback of Ag metallization. Ag(Al) thin films show good thermal stability on SiO2 layer without any diffusion barrier. The films are stable up to 600 °C for 1 hour in vacuum. Electrical resistivity of as-deposited Ag (5 at % Al) thin film is slightly higher than that of pure Ag thin film. However, the resistivity of Ag(Al) samples annealed at high temperatures (up to 600 °C for 1 hour in vacuum) remains constant due to the improvement of thermal stability (large reduction of agglomeration). This finding can impact metallization for thin film transistors (TFT) for displays, including flexible displays, and high-speed electronics due to lower resistivity value compared to Cu thin film.

Free-standing Cu- and Ni-line patterns with varying line dimensions in the range of a few micrometers were manufactured by means of electrodeposition through a lithographically prepared mask. XRD studies revealed for Cu-lines a pronounced influence of the pattern geometry on crystallographic texture and peak broadening. Information on the strain distribution within individual Cu-lines was obtained from FEM.

The interactions of sputter-deposited ruthenium with organosilicate glass (OSG) at 300 K have been studied by x-ray photoelectron spectroscopy (XPS) for Ru coverages from ∼ 0.1 monolayer to several monolayers, using in-situ sample transfer between the deposition and analysis chambers. The results indicate Stranski-Krastanov (SK) type growth, with the completion of the first layer of Ru at an average thickness corresponding to 1 monolayer average coverage. Ru(0) is the only electronic state present. XPS core level spectra indicate weak chemical interactions between Ru and the substrate. A less pronounced tendency towards SK growth was observed for Ru deposition on parylene. Deposition of Ru on OSG followed by electroless deposition of Cu resulted in the formation of a shiny copper film that failed the Scotch Tape test. Results indicate failure mainly at the Ru/OSG interface.

The increasing demand for faster and more reliable integrated circuits (ICs) has promoted the integration of Copper-based metallization. Electroplated Cu films demonstrate a microstructural transition at room temperature, known as self annealing. In this paper we intend to investigate the annealing behavior of electroplated Cu films grown on a seed Cu layer on top of the barrier layers over a single crystal silicon substrate. All the samples were undergone through a multistep annealing process. Grazing incident x-ray diffraction pattern shows stronger x-ray reflections from Cu (111) and (220) planes but weaker reflections from (200), (311) and (222) planes in all the electroplated Cu samples. Transmission electron microscopy was performed on the cross section of the samples and the diffraction pattern showed the crystalline behavior of both seed layer and electroplated Cu. Nanoindentation was performed on all the samples using the continuous stiffness measurement (CSM) technique and it was found that the elastic modulus varies from 110 to 130 GPa while the hardness varies from 1 to 1.6 GPa depending on the annealing conditions. The tribological properties of all the copper films were also measured using the Bench Top CMP tester. Subsequently, Nanoindentation was performed on the samples after polishing the top surface in order to investigate the work hardening and an increase in hardness and modulus was observed. Finite Element Modeling was performed in order to investigate the stress behavior during nanoindentation.

We have developed platinum (Pt) deposition and chlorine-based Reactive Ion Etch (RIE) processes that are needed to deposit, pattern and embed electrodes deep within a MEMS process flow. Various combinations of chlorinebased gases were tested to find the optimum gas mixture for RIE. A 1: 0.4 mixture ratio of pure chlorine to argon and 100-150 Watts of RF microwave power were found to be optimum conditions for the RIE of platinum metal. The addition of argon gas to chlorine was found to contribute to the anisotropic etching of platinum, obtaining vertical shaped sidewall patterns. A simple model of the platinum etching mechanism is proposed. Following the plasma enhanced formation of platinum and chlorine ions, volatile products of platinum chlorides were formed and driven away at elevated temperature. As a demonstration of our RIE process, micron-sized platinum patterns with vertical sidewalls were fabricated. Etch chemistry was investigated using ToF SIMS analysis. This etch technique will be useful to device developers intending to use the unique properties of platinum metal as an electrode that is deeply embedded within a MEMS process flow.

Pulsed metalorganic chemical vapor deposition (MOCVD) of conformal copper seed layers, for the electrodeposition Cu films, has been achieved by an alternating supply of a Cu(I) source and H2 reactant at the deposition temperatures of 50 - 100°C. The Cu thickness increased proportionally to the number of cycle, and the growth rate was in the range of 3.5 to 8.2 A /cycle, showing the ability to control the nano-scale thickness. As-deposited films show highly smooth surfaces even for more than 100nm. In addition, about a 90% step coverage was obtained inside trenches, with an aspect ratio greater than 30:1. H2, introduced as a reactant gas, can play an active role in achieving highly conformal coatings, with increased grain sizes.

Copper films were prepared at room temperature under a Cu(hfac)2-Ar-H2 atmosphere in order toobtain metallized plastics by using ECR-MOCVD (Electron Cyclotron Resonance Metal OrganicChemical Vapor Deposition) coupled with a DC bias system. Structural analysis of the films byECR showed that fine copper grains were embedded in an amorphous plastic matrix with goodadherence. Considering the AES result of the film prepared by ECR-CVD, we construe that thecopper film is chemically bonded with a plastic substrate. The delamination force determined bythe nano-scratch tester® showed in the range from 10 to 20mN.

The application of porous low-k interlayer dielectrics is needed for reducing the parasitical capacitance, especially at 65-nm node and beyond. The understanding of process-induced modifications to material properties is crucial for a successful integration of these low-k dielectrics. The dry etching processes of porous low-k materials are important modules in ULSI fabrication. In this study, the interaction between MSQ-based JSR LKD-5109 films (shown by PALS to have interconnected 2.8 nm size pores) with CF4/O2 plasma has been investigated. Various ratios of O2 content were designed to characterize its effects on the etch rate, formation of polymerization layer, and properties of the LKD-5109 film. Composition analysis was conducted by SIMS and FTIR. Moisture absorption and fluorine diffusion into low-k films after etch process are observed, along with carbon depletion near the surface region. The influence of etching chemistries on the morphological characteristics of thin Ta barrier layers (8-nm in thickness) deposited on etched low-k films were further investigated by SEM, and it is found that oxygen concentration has significant influences on the morphological characteristics of thin Ta barriers.

Wafer-level three-dimensional (3D) integration as an emerging architecture for future chips offers high interconnect performance by reducing delays of global interconnects and high functionality with heterogeneous integration of materials, devices, and signals. Various 3D technology platforms have been investigated, with different combinations of alternative alignment, bonding, thinning and inter-wafer interconnection technologies. Precise alignment on the wafer level is one of the key challenges affecting the performance of the 3D interconnects. After a brief overview of the wafer-level 3D technology platforms, this paper focuses on waferto-wafer alignment fundamentals. Various alignment methods are reviewed. A higher emphasis lies on the analysis of the alignment accuracy. In addition to the alignment accuracy achieved prior to bonding, the impacts of wafer bonding and subsequent wafer thinning will be discussed.

Increasing the elastic modulus and hardness of low K films is one of the key challenges towards integration of these materials into future integrated circuits. Several approaches are explored for increasing the hardness of carbon doped oxide (CDO) dielectrics. Several low K precursors and their mixtures specifically chosen to enhance the hardness (H) and modulus (E) of CDO films through chemically induced cross-linking. Composition and FTIR measurements suggest the presence of C-C and C-Si cross-linking with concurrent observation of improved film hardness and modulus at relatively low deposition temperatures. Films deposited at 373°C using diethoxy-methyl-oxiranyl have a hardness and modulus of 2.5 GPa and 18.1 GPa respectively. Films deposited at 180°C using tetramethylcyclotetrasiloxane (TMCTS) and 25% hardener have hardness and modulus of 1.5 GPa and 9.4 GPa, respectively. These film properties are significantly higher than those observed for TMCTS alone under similar deposition conditions. Based on these results a low temperature process with 25% hardener and 75% TMCTS combined with a porogen was used to produce a porous film with a k<2.5 and a hardness of 0.72GPa.