Skip to main content Accessibility help

We use cookies to distinguish you from other users and to provide you with a better experience on our websites. Close this message to accept cookies or find out how to manage your cookie settings.

Close cookie message
×
Hostname: page-component-84b7d79bbc-g7rbq Total loading time: 0 Render date: 2024-07-28T03:51:18.059Z Has data issue: false hasContentIssue false

7 - Graphene and 2D crystal tunnel transistors

from Section II - Tunneling devices

Published online by Cambridge University Press:  05 February 2015

By
Qin Zhang ,
Pei Zhao ,
Nan Ma ,
Grace (Huili) Xing  and
Debdeep Jena
Edited by
Tsu-Jae King Liu  and
Kelin Kuhn
Qin Zhang
Affiliation:
University of Notre Dame
Pei Zhao
Affiliation:
University of Notre Dame
Nan Ma
Affiliation:
University of Notre Dame
Grace (Huili) Xing
Affiliation:
University of Notre Dame
Debdeep Jena
Affiliation:
University of Notre Dame
Tsu-Jae King Liu
Affiliation:
University of California, Berkeley
Kelin Kuhn
Affiliation:
Cornell University, New York
Get access

Summary

What is a low-power switch?

Transistors in the traditional field effect geometry operate by the injection of mobile carriers – electrons or holes – from a source reservoir to the drain reservoir through a conducting channel region. The carriers enter the channel region by surmounting an electrostatic potential barrier. The gate electrode controls the height of this barrier capacitively. The carriers in the source reservoir are in thermal equilibrium with the source contact. This means that the carriers, say electrons, are distributed in energy in the conduction band according to the Fermi–Dirac distribution f(E = 1/1[1+exp((E − EF)/kT)]. The Maxwell–Boltzmann approximation f(E) ~ exp[− E/kT] of the Fermi–Dirac distribution for large energies represents the high-energy tail of the distribution. There are electrons in this tail with energy higher than the potential barrier; the gate cannot stop them from being injected into the channel. This leads to a sub-threshold “leakage” drain current ID ~ exp[qVGS / kT], which leads to the well-known sub-threshold slope (S) requirement of S ~ (kT / q)ln10 ~ 60 mV/dec change of current. Methods to make the SS steeper than the 300 K value of 60 mV/dec value are expected to substantially lower the power dissipation in digital logic and computation [1, 2]. The methods must explore novel mechanisms of charge transport, or of electrostatic gating. This chapter focuses on transport.

The high-energy tail of electrons exists because of the available density of states (DOS) DC(E) of the conduction band; the electron distribution in energy is n(E) = DC(E)f(E). If the DOS were cut off, there would be no tail, and it is possible to obtain S less than 60 mV/dec. This sort of energy filtering is possible if we replace the n-type source for electrons by a p-type source, which has a valence band maximum and zero DOS above. For injection into the channel of the n-FET, the electrons cannot undergo the traditional drift/diffusion process, but have to quantum mechanically tunnel through the bandgap. This energy-filtering scheme to achieve sub-60 mV/dec switching is the central idea behind the tunneling FET (or TFET).

Type
Chapter
Information
CMOS and Beyond
Logic Switches for Terascale Integrated Circuits
 , pp. 144 - 174
Publisher: Cambridge University Press
Print publication year: 2015

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

Moore, G. E., “Cramming more components onto integrated circuits.” Electronics, 114–117 (1965).
Shahidi, G. G., “Device scaling for 15 nm node and beyond.” In Device Research Conference, 2009. DRC 2009, pp. 247–250 (2009).
Appenzeller, J., Lin, Y.-M., Knoch, J., & Avouris, Ph., “Band-to-band tunneling in carbon nanotube field-effect transistors.” Physics Review Letters, 93(19), 196805 (2004).CrossRefGoogle ScholarPubMed
Jena, D., Fang, T., Zhang, Q., & Xing, H., “Zener tunneling in semiconducting nanotube and graphene nanoribbon p-n junctions.” Applied Physics Letters, 93, 112106 (2008).CrossRefGoogle Scholar
Zhang, Q., Fang, T., Xing, H. L., Seabaugh, A., & Jena, D., “Graphene nanoribbon tunnel transistors.” IEEE Electron Device Letters, 29, 1344–1346 (2008).CrossRefGoogle Scholar
Zhang, Q., Lu, Y. Q., Xing, H. G., Koester, S. J., & Koswatta, S. O., “Scalability of atomic-thin-body (ATB) transistors based on graphene nanoribbons.” IEEE Electron Device Letters, 31, 531–533 (2010).CrossRefGoogle Scholar
Luisier, M. & Klimeck, G., “Performance analysis of statistical samples of graphene nanoribbon tunneling transistors with line edge roughness.” Applied Physics Letters, 94, 223505 (2009).CrossRefGoogle Scholar
Chin, S.-K., Seah, D., Lam, K.-T., Samudra, G. S., & Liang, G., “Device physics and characteristics of graphene nanoribbon tunneling FETs.” IEEE Transactions on Electron Devices, 57, 3144–3152 (2010).CrossRefGoogle Scholar
Koswatta, S. O., Lundstrom, M. S., & Nikonov, D. E., “Performance comparison between p-i-n tunneling transistors and conventional MOSFETs.” IEEE Transactions on Electron Devices, 56, 456–464 (2009).CrossRefGoogle Scholar
Zhang, Q., Lu, Y., Richter, C. A., Jena, D., & Seabaugh, A., “Optimum band gap and supply voltage in tunnel FETs.” submitted to IEEE Transactions on Electron Devices (2014).
Frank, D. J., Taur, Y., & Wong, H.-S. P., “Generalized scale length for two dimensional effects in MOSFETs.” IEEE Electron Device Letters, 19, 385–387 (1998).CrossRefGoogle Scholar
Liang, X. & Taur, Y., “A 2-D analytical solution for SCEs in DG MOSFETs.” IEEE Transactions on Electron Devices, 51, 1385–1391 (2004).CrossRefGoogle Scholar
Zhang, Q., Ye, L., Xing, G. H., Richter, C. A., Koester, S. J., & Koswatta, S. O., “Graphene nanoribbon Schottky-barrier FETs for end-of-the-roadmap CMOS: challenges and opportunities.” In Device Research Conference, 2010. DRC 2010, pp. 75–76 (2010).
Ma, N. & Jena, D., “Interband tunneling in two-dimensional crystal semiconductors.” Applied Physics Letters 102, 132102 (2013).CrossRefGoogle Scholar
Seabaugh, A. C. & Zhang, Q., “Low-voltage tunnel transistors for beyond CMOS logic.” Proceedings of the IEEE 98, 2095 (2010).CrossRefGoogle Scholar
Ma, N. & Jena, D., “Interband tunneling transport in 2-dimensional crystal semiconductors.” In Device Research Conference, 2013. DRC 2013, pp. 103–104 (2013).
Fiori, G. & Iannaccone, G., “Ultralow-voltage bilayer graphene tunnel FET.” IEEE Electron Device Letters, 30, 1096 (2009).CrossRefGoogle Scholar
Lam, K.-T., Cao, X., & Guo, J., “Device performance of heterojunction tunneling field-effect transistors based on transition metal dichalcogenide monolayer.” IEEE Electron Device Letters, 34, 1331–1333 (2013).CrossRefGoogle Scholar
Fiori, G., Betti, A., Bruzzone, S., & Iannaccone, G., “Lateral graphene-hBCN heterostructures as a platform for fully two-dimensional transistors.” ACS Nano, 6, 2642–2648 (2012).CrossRefGoogle ScholarPubMed
Feenstra, R. M., Jena, D., & Gu, G., “Single-particle tunneling in doped graphene-insulator-graphene junctions.” Journal of Applied Physics, 111, 043711 (2012).CrossRefGoogle Scholar
Zhao, Pei, Feenstra, R.M., Gu, Gong, & Jena, D.. “SymFET: a proposed symmetric graphene tunneling field effect transistor.” IEEE Transactions on Electron Devices, 60(3), 951–957 (2013).CrossRefGoogle Scholar
Lee, G.-H. et al., “Electron tunneling through atomically flat and ultrathin hexagonal boron nitride.” Applied Physics Letters, 99, 243114 (2011).CrossRefGoogle Scholar
Banerjee, S. K., Register, L. F., Tutuc, E., Reddy, D., & MacDonald, A. H., “Bilayer pseudospin field-effect transistor (BiSFET): a proposed new logic device.” IEEE Electron Device Letters, 30, 158 (2009).CrossRefGoogle Scholar
Eisenstein, J. P., Pfeiffer, L. N., & West, K. W., “Field-induced resonant tunneling between parallel two-dimensional electron systems.” Applied Physics Letters 58, 1497 (1991).CrossRefGoogle Scholar
Eisenstein, J. P., Gramila, T. J., Pfeiffer, L. N., & West, K. W., “Probing a two-dimensional Fermi surface by tunneling.” Physics Reviews B 44, 6511 (1991).CrossRefGoogle ScholarPubMed
Simmons, J. A. et al., “Planar quantum transistor based on 2D–2D tunneling in double quantum well heterostructures.” Journal of Applied Physics 84(10), 5626–5634 (1998).CrossRefGoogle Scholar
Britnell, L. et al., “Resonant tunnelling and negative differential conductance in graphene transistors.” Nature Communications 4, 1794 (2013).CrossRefGoogle ScholarPubMed
Britnell, L. et al., “Field-effect tunneling transistor based on vertical graphene heterostructures.” Science, 335, 947 (2012).CrossRefGoogle ScholarPubMed
Georgiou, T., Jalil, R., Belle, B. D. et al., “Vertical field-effect transistor based on graphene–WS2 heterostructures for flexible and transparent electronics.” Nature Nanotechnology 8, 100–103 (2013).CrossRefGoogle ScholarPubMed
Gu, G. et al., “Field effect in epitaxial graphene on a silicon carbide substrate.” Applied Physics Letters, 90, 253507 (2007).CrossRefGoogle Scholar
Moon, J. S. et al., “Epitaxial-graphene RF field-effect transistors on Si-face 6H-SiC substrates.” IEEE Electron Device Letters, 30, 650–652 (2009).CrossRefGoogle Scholar
Li, X. et al., “Large-area synthesis of high-quality and uniform graphene films on copper foils.” Science, 324, 1312–1314 (2009).CrossRefGoogle ScholarPubMed
Song, L. et al., “Large scale growth and characterization of atomic hexagonal boron nitride layers.” Nano Letters, 10, 3209–3215 (2010).CrossRefGoogle ScholarPubMed
Lee, Y. H. et al., “Synthesis of large-area MoS2 atomic layers with chemical vapor deposition.” Advanced Materials., 24, 2320–2325 (2012).CrossRefGoogle ScholarPubMed
Hwang, W. S. et al., “Transistors with chemically synthesized layered semiconductor WS2 exhibiting 105 room temperature modulation and ambipolar behavior.” Applied Physics Letters, 101, 013107 (2012).CrossRefGoogle Scholar
Li, R. et al. “AlGaSb/InAs tunnel field-effect transistor with on-current of 78μA/μm at 0.5V.” IEEE Electron Device Letters, 33(3), 363–365 (2012).CrossRefGoogle Scholar
Kang, J., Tongay, S., Zhou, J., Li, J., & Wu, J.. “Band offsets and heterostructures of two-dimensional semiconductors.” Applied Physics Letters, 102(1), 012111 (2013).CrossRefGoogle Scholar

Save book to Kindle

To save this book to your Kindle, first ensure coreplatform@cambridge.org is added to your Approved Personal Document E-mail List under your Personal Document Settings on the Manage Your Content and Devices page of your Amazon account. Then enter the ‘name’ part of your Kindle email address below. Find out more about saving to your Kindle.

Note you can select to save to either the @free.kindle.com or @kindle.com variations. ‘@free.kindle.com’ emails are free but can only be saved to your device when it is connected to wi-fi. ‘@kindle.com’ emails can be delivered even when you are not connected to wi-fi, but note that service fees apply.

Find out more about the Kindle Personal Document Service.

Available formats
×

Save book to Dropbox

To save content items to your account, please confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account. Find out more about saving content to Dropbox.

Available formats
×

Save book to Google Drive

To save content items to your account, please confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account. Find out more about saving content to Google Drive.

Available formats
×