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A low temperature amorphous zinc indium oxide (ZIO) thin film transistor (TFT) backplane technology for high information content flexible organic light emitting diode (OLED) displays has been developed. We have fabricated 4.1-in. diagonal OLED backplanes on the Flexible Display Center’s six-inch wafer-scale pilot line using ZIO as the active layer. The ZIO based TFTs exhibited an effective saturation mobility of 18.6 cm2/V-s and a threshold voltage shift of 2.2 Volts or less under positive and negative gate bias DC stress for 10000 seconds. We report on the critical steps in the evolution of the backplane process: the qualification of the low temperature (200°C) ZIO process, the stability of the devices under forward and reverse bias stress, the transfer of the process to flexible plastic substrates, and the fabrication of white organic light emitting diode (OLED) displays.
Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used in many areas and the most important application is in active matrix liquid crystal display. However, the instability of the a-Si:H TFTs constrains their usability. These TFTs have been annealed at higher temperatures in hope of improving their electrical performance. But, higher anneal temperatures become a constraint when the TFTs are grown on polymer-based flexible substrates. This study investigates the effect of anneal time on the performance of the a-Si:H TFTs on PEN. Thin-film transistors are annealed at different anneal times (4 h, 24 h, and 48 h) and were stressed under different bias conditions. Sub-threshold slope and the off-current improved with anneal time. Off-current was reduced by two orders of magnitude for 48 hours annealed TFT and sub-threshold slope became steeper with longer annealing. At positive gate-bias-stress (20 V), threshold voltage shift (∆Vt) values are positive and exhibit a power-law time dependence. High temperature measurements indicate that longer annealed TFTs show improved performance and stability compared to unannealed TFTs. This improvement is due to reduction of interface trap density and good a-Si:H/insulator interface quality with anneal time.
Principal challenges to direct fabrication of high performance a-Si:H transistor arrays on flexible substrates include automated handling through bonding-debonding processes, substrate-compatible low temperature fabrication processes, management of dimensional instability of plastic substrates, and planarization and management of CTE mismatch for stainless steel foils. In collaboration with our industrial and academic partners, we have developed viable solutions to address these challenges, as described in this paper.
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