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Threshold Voltage Shift Variation of a-Si:H TFTs With Anneal Time

Published online by Cambridge University Press:  01 February 2011

Anil Indluru
Affiliation:
anil.reddy@asu.edu, Arizona State University, Tempe, Arizona, United States
Sameer M Venugopal
Affiliation:
Sameer.Venugopal@asu.edu, Flexible Display Center, Tempe, Arizona, United States
David R Allee
Affiliation:
allee@asu.edu, Arizona State University, Tempe, Arizona, United States
Terry L Alford
Affiliation:
TA@asu.edu, Arizona State University, 1711 S Rural Rd, ERC 252, Tempe, 85281, United States
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Abstract

Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used in many areas and the most important application is in active matrix liquid crystal display. However, the instability of the a-Si:H TFTs constrains their usability. These TFTs have been annealed at higher temperatures in hope of improving their electrical performance. But, higher anneal temperatures become a constraint when the TFTs are grown on polymer-based flexible substrates. This study investigates the effect of anneal time on the performance of the a-Si:H TFTs on PEN. Thin-film transistors are annealed at different anneal times (4 h, 24 h, and 48 h) and were stressed under different bias conditions. Sub-threshold slope and the off-current improved with anneal time. Off-current was reduced by two orders of magnitude for 48 hours annealed TFT and sub-threshold slope became steeper with longer annealing. At positive gate-bias-stress (20 V), threshold voltage shift (∆Vt) values are positive and exhibit a power-law time dependence. High temperature measurements indicate that longer annealed TFTs show improved performance and stability compared to unannealed TFTs. This improvement is due to reduction of interface trap density and good a-Si:H/insulator interface quality with anneal time.

Type
Research Article
Copyright
Copyright © Materials Research Society 2010

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