The operation of a MOSFET transistor fabricated in undoped, small-grain polysilicon is considered, and a model is developed which can predict threshold and drain current as a function of gate voltage. A two-dimensional calculation is described for the band-bending under the influence of a gate potential with the assumption that the grain boundaries are repetitive and oriented at right angles to the gate-oxide/polysilicon interface. Both hole and electron traps are assumed present at the grain boundaries and are coincident in energy with the intrinsic Fermi level at room temperature. An energy barrier to the flow of carriers is present in the undoped polysilicon, and the magnitude of this energy barrier is dependent on the gate voltage. The band-bending occurs over much shorter distances than the intrinsic Debye length, and the trapped charge at the grain boundaries behaves very similarly to the charged impurities in a depletion model. The two-dimensional model can be approximated by a one-dimensional calculation for the band-bending by making the assumption that the trapped charge is uniformly distributed throughout the grain. The results of this calculation can be used to calculate the magnitude of the free carriers in the channel region. Using this information, the dependence of the potential barrier on gate voltage, and the gradual channel approximation for an FET, one can compute the drain current vs. gate voltage, and the results of these calculations are given for parameters used in fabricating actual devices. Finally, experimental results are compared with the model for typical transistors fabricated in undoped, small-grain polysilicon.