Instruction partitioning for pipelining

In Section 4.3 we learned that the execution of a processor instruction consists of two basic steps: fetching the instruction from memory, and then executing it. In the simplest implementation of a processor, the complete fetch-execute cycle would be completed for one instruction before the next one begins. We saw this type of one-instruction-at-a-time operation in the algorithmic behavioral model in Chapter 4. To speed up the execution of instructions, however, we can break the fetch-execute cycle into several simpler sub-operations. We then can overlap the execution of different instructions in an assembly line fashion where each step in the assembly line is dedicated to performing one specific operation for each instruction. This assembly line processing is called pipelining.

The first step in designing a pipeline for a processor is to determine the smaller sub-operations within the fetch-execute cycle that must be performed to execute an instruction. For the VeSPA processor, each instruction will perform some of the following sub-operations, although not all of the instructions will perform all of the operations:

• Fetch the instruction from memory.

• Increment the program counter.

• Fetch the operands from the registers.

• Compute a memory address.

• Read an operand from memory.

• Write a result to the memory or to a register.

The next step in designing the pipeline for VeSPA, or for any other processor ISA, is to determine how these individual operations should be partitioned into the different stages of the pipeline.