A new double-layered stacked LSI fabrication process has been developed for the purpose of realizing short fabrication turn-around time, high fabrication yield and high integration density. This process, which is named “Elemental Level Vertical Integrated Circuit (ELVIC)” technology, puts 2 convenfionally made LSI chips face to face andbonds them by thermal compression. The process includes, in addition to the conventionalLSI fabrication process, vertical interconnection (VI) formation in the upper and lower LSI layers, planarization of both upper and lower layer surfaces, and inter-level connections using pressure and heat. In the experimental version, about 52,000 10 x 10 μm2 Au-on-Ti VIs were connected on a 5 x 5 mm2 chip. Each pair of mated VIs is measured for tensile strength of 4 mg force. A 2-layer, 31-stage inter- CMOS/bulk ring oscillator consisting of p-channel MOSFETs on the upppr layerand nchannel MOSFETs on the lower layer has been built. Propagation delay time per stageis 1.86 nsec at the supply voltage of 5 V. ELVIC technology can produce a variety of benefits such as high production yield, doubling integration density, latch-up free CMOS LSIs, radiation damage free LSls, multi-function, and complete mixing of bipolar, CMOS andGaAs technologies.